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learn:programmable-logic:tutorials:arty-getting-started-with-microblaze:start [2017/02/03 22:30] – [Prerequisites] sbobrowiczlearn:programmable-logic:tutorials:arty-getting-started-with-microblaze:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Arty - Getting Started with Microblaze ====== ====== Arty - Getting Started with Microblaze ======
 +
 +<WRAP round important 660px>
 +=== Important! ===
 +This guide is obsolete, the updated guide can be found [[:vivado:getting-started-with-ipi:start|here]].
 +</WRAP>
  
 {{ :arty:arty-obl-1000.png?nolink&500 |}} {{ :arty:arty-obl-1000.png?nolink&500 |}}
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   * Displayed the final output on both the SDK console and Tera Term   * Displayed the final output on both the SDK console and Tera Term
  
------ 
  
-===== Prerequisites ===== +==== Introduction to MicroBlaze ====
- +
-=== Skills === +
-  * **Familiarity with Vivado** +
-  * **Block Design Experience** +
- +
-=== Hardware === +
-  * **Digilent Arty FPGA Board** +
-  * **Micro USB Cable** +
-    * //Used for UART communication, JTAG programming, and Power// +
- +
-=== Software === +
-  * **Xilinx Vivado 2015.4 with the SDK package.**  +
-    * //Newer versions of Vivado may also work// +
-  * **Digilent Board Support Files** +
-    * //Follow the **[[vivado:boardfiles|wiki guide]]** on how to install Board Support Files for Vivado 2015.X// +
- +
------ +
- +
- +
-===== Introduction =====+
  
 Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool.  Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool. 
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 Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Arty. Finally, a UART ( universal asynchronous receiver/transmitter ) IP block will be added to communicate between the host PC and the soft processor core running on the Arty.
  
------+==== General MicroBlaze Design Flow ====
  
-===== General Design Flow ===== +**I. Vivado** 
- +
-I. Vivado +
  
   * Open Vivado and select Arty board   * Open Vivado and select Arty board
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 We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.
  
-II. SDK+**II. SDK**
  
   * Create new application project and select default Hello World template   * Create new application project and select default Hello World template
   * Program FPGA   * Program FPGA
   * Run configuration by selecting the correct UART COM Port and Baud Rate   * Run configuration by selecting the correct UART COM Port and Baud Rate
 +
 +-----
 +
 +===== Prerequisites =====
 +
 +=== Skills ===
 +  * **Familiarity with Vivado**
 +  * **Block Design Experience**
 +
 +=== Hardware ===
 +  * **Digilent Arty FPGA Board**
 +  * **Micro USB Cable**
 +    * //Used for UART communication, JTAG programming, and Power//
 +
 +=== Software ===
 +  * **Xilinx Vivado 2015.4 with the SDK package.** 
 +    * //Newer versions of Vivado may also work//
 +  * **Digilent Board Support Files**
 +    * //Follow the **[[vivado:boardfiles|wiki guide]]** on how to install Board Support Files for Vivado 2015.X//
  
 ----- -----
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 >{{:genesys2:gsmb27.jpg?nolink&500|}} >{{:genesys2:gsmb27.jpg?nolink&500|}}
  
-{{tag>learn programmable-logic tutorial arty microblaze}}+/*{{tag>learn programmable-logic tutorial arty microblaze}}*/