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 ====== Lab 4d: Communications - I2C Serial Protocols ====== ====== Lab 4d: Communications - I2C Serial Protocols ======
 +[[{}/learn/courses/unit-4-1/start|Back to Unit 4 Part 1]]
 +[[{}/learn/courses/unit-4-2/start|Back to Unit 4 Part 2]]
 +[[{}/learn/courses/unit-4-lab4c/start|Back to Lab 4c]]
  
 === Download This Document === === Download This Document ===
-  * {{ :learn:courses:unit-4-lab4d:lab_4d.pdf |Lab 4d PDF}}+{{ :learn:courses:unit-4-lab4d:lab_4d.pdf |Lab 4d PDF}}
  
  
 ===== 1. Objectives ===== ===== 1. Objectives =====
-  * Develop a library of functions that manage the functionality and retrieve data from a three-axis accelerometer using I²C communications. +  - Develop a library of functions that manage the functionality and retrieve data from a three-axis accelerometer using I²C communications. 
-  * Display the accelerometer data on the Basys MX3 LCD. +  - Display the accelerometer data on the Basys MX3 LCD. 
-  * Display the accelerometer data on the workstation monitor using UART asynchronous communications.+  - Display the accelerometer data on the workstation monitor using UART asynchronous communications.
  
 ---- ----
  
 ===== 2. Basic Knowledge ===== ===== 2. Basic Knowledge =====
-  * How to exchange serial data with a computer terminal using the PIC32MX370 UART +  - How to exchange serial data with a computer terminal using the PIC32MX370 UART 
-  * How to use the PIC32MX3270 processor to display text on a character LCD +  - How to use the PIC32MX3270 processor to display text on a character LCD 
-  * How to implement code reuse that integrates previously developed processor code into new application projects. +  - How to implement code reuse that integrates previously developed processor code into new application projects. 
  
  
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 ===== 3. Equipment List ===== ===== 3. Equipment List =====
 ==== 3.1. Hardware ==== ==== 3.1. Hardware ====
-  * [[http://store.digilentinc.com/basys-mx3-pic32mx-trainer-board-recommended-for-embedded-systems-courses/|Basys MX3 trainer board]] +  - [[https://digilent.com/shop/basys-mx3-pic32mx-trainer-board-for-embedded-systems-courses/|Basys MX3 trainer board]] 
-  * Workstation computer running Windows 10 or higher, MAC OS, or Linux +  - Workstation computer running Windows 10 or higher, MAC OS, or Linux 
-  * 2 [[http://store.digilentinc.com/usb-a-to-micro-b-cable/|Standard USB A to micro-B cables]]+  - 2 [[https://digilent.com/shop/usb-a-to-micro-b-cable/|Standard USB A to micro-B cables]]
  
 In addition, we suggest the following instruments: In addition, we suggest the following instruments:
-  * [[http://store.digilentinc.com/analog-discovery-2-100msps-usb-oscilloscope-logic-analyzer-and-variable-power-supply/|Analog Discovery 2]]+  - [[https://digilent.com/shop/analog-discovery-2-100ms-s-usb-oscilloscope-logic-analyzer-and-variable-power-supply/|Analog Discovery 2]]
  
 ==== 3.2. Software ==== ==== 3.2. Software ====
 The following programs must be installed on your development work station: The following programs must be installed on your development work station:
  
-  * [[http://www.microchip.com/mplab/mplab-x-ide|Microchip MPLAB X® v3.35 or higher]] +  - [[http://www.microchip.com/mplab/mplab-x-ide|Microchip MPLAB X® v3.35 or higher]] 
-  * [[http://www.microchip.com/SWLibraryWeb/product.aspx?product=PIC32%20Peripheral%20Library|PLIB Peripheral Library]] +  - [[http://www.microchip.com/SWLibraryWeb/product.aspx?product=PIC32%20Peripheral%20Library|PLIB Peripheral Library]] 
-  * [[http://www.microchip.com/xcdemo/xcpluspromo.aspx|XC32 Cross Compiler]] +  - [[http://www.microchip.com/xcdemo/xcpluspromo.aspx|XC32 Cross Compiler]] 
-  * [[http://store.digilentinc.com/waveforms-2015-download-only/|WaveForms 2015]]  +  - [[https://digilent.com/shop/software/digilent-waveforms/|WaveForms]]  
-  * [[http://www.putty.org/|PuTTY Terminal Emulation]]+  - [[http://www.putty.org/|PuTTY Terminal Emulation]]
  
 ---- ----
  
 ===== 4. Project Takeaways ===== ===== 4. Project Takeaways =====
-  * Understanding of requirements and implementations of synchronous communications. +  - Understanding of requirements and implementations of synchronous communications. 
-  * Understanding of the I²C Protocol. +  - Understanding of the I²C Protocol. 
-  * Understand the advantages and disadvantages of I2C compared to UART and SPI.+  - Understand the advantages and disadvantages of I2C compared to UART and SPI.
  
  
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 Figure 5.1 shows the general format of an I²C message. There are two signals used in the I²C protocol: the serial clock signal (SCL) and the serial data signal (SDA). Other than the start and stop sequences, the SDA is not allowed to change states while the SCL signal is high. When the I²C communications is in an idle state, both the SCL and the SDA signals are in the high state. Figure 5.1 shows the general format of an I²C message. There are two signals used in the I²C protocol: the serial clock signal (SCL) and the serial data signal (SDA). Other than the start and stop sequences, the SDA is not allowed to change states while the SCL signal is high. When the I²C communications is in an idle state, both the SCL and the SDA signals are in the high state.
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-1.png?nolink&600 |Figure 5.1.  Waveform showing the clock and data timing for an I²C message.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-1.png?nolink&800 |Figure 5.1.  Waveform showing the clock and data timing for an I²C message.}}
 //Figure 5.1.  Waveform showing the clock and data timing for an I²C message.// //Figure 5.1.  Waveform showing the clock and data timing for an I²C message.//
  
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 I²C networks consist of a data signal (SDA) and a clock signal (SCL) that have a common reference – usually digital ground. A [[http://en.wikipedia.org/wiki/Pull-up_resistor|pull-up resistor]] to VDD is required to be connected to each signal line. Both clock and data signals are connected in a [[http://en.wikipedia.org/wiki/Wired_logic_connection|wired-AND]] configuration that require [[http://en.wikipedia.org/wiki/Open_collector|open collector]] (also called open drain for CMOS transistors) outputs from both master and slave devices. The output of both devices must be in the open collector state for the signal line to be in the high state (also called the [[http://www.weedtech.com/an100.pdf|recessive state]]). The SDA or SCL line is low if the output transistor of either the master or any slave device pulls the signal low. The low state is also referred to as the dominant state. As shown in Fig. 5.2, both slave and master devices can always determine the state of the SCL or SDA lines by reading the value of the output pin.   I²C networks consist of a data signal (SDA) and a clock signal (SCL) that have a common reference – usually digital ground. A [[http://en.wikipedia.org/wiki/Pull-up_resistor|pull-up resistor]] to VDD is required to be connected to each signal line. Both clock and data signals are connected in a [[http://en.wikipedia.org/wiki/Wired_logic_connection|wired-AND]] configuration that require [[http://en.wikipedia.org/wiki/Open_collector|open collector]] (also called open drain for CMOS transistors) outputs from both master and slave devices. The output of both devices must be in the open collector state for the signal line to be in the high state (also called the [[http://www.weedtech.com/an100.pdf|recessive state]]). The SDA or SCL line is low if the output transistor of either the master or any slave device pulls the signal low. The low state is also referred to as the dominant state. As shown in Fig. 5.2, both slave and master devices can always determine the state of the SCL or SDA lines by reading the value of the output pin.  
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-2.png?nolink&4600 |Figure 5.2. Circuit diagram of I²C device pins.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-2.png?nolink&400 |Figure 5.2. Circuit diagram of I²C device pins.}}
 //Figure 5.2. Circuit diagram of I²C device pins.// //Figure 5.2. Circuit diagram of I²C device pins.//
  
 As stated above, the SDA should not change levels while the SCL is high except to implement the START and STOP sequences. As illustrated in Fig. 5.3, a start sequence is generated when the SDA line makes a recessive to dominant transition when the SCL line is in the recessive state. Figure 5.4 shows that a STOP sequence is generated when the SDA signal transitions from the dominant state to the recessive state while the SCL line is in the recessive state. Figure 5.5 shows that data is either written to the slave or read from the slave during the period identified as 2 to 3. The master or slave (depending on whether it is a write or read operation) is allowed to change the state of the SDA line while the SCL line is in the dominant state, identified as 1 and 4 in Fig. 5.5. Figure 5.6 shows an acknowledge sequence that is generated by the slave after the master writes a byte of data, or is generated by the master after the master reads a byte of data from the slave. As stated above, the SDA should not change levels while the SCL is high except to implement the START and STOP sequences. As illustrated in Fig. 5.3, a start sequence is generated when the SDA line makes a recessive to dominant transition when the SCL line is in the recessive state. Figure 5.4 shows that a STOP sequence is generated when the SDA signal transitions from the dominant state to the recessive state while the SCL line is in the recessive state. Figure 5.5 shows that data is either written to the slave or read from the slave during the period identified as 2 to 3. The master or slave (depending on whether it is a write or read operation) is allowed to change the state of the SDA line while the SCL line is in the dominant state, identified as 1 and 4 in Fig. 5.5. Figure 5.6 shows an acknowledge sequence that is generated by the slave after the master writes a byte of data, or is generated by the master after the master reads a byte of data from the slave.
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-3.png?nolink&600 |Figure 5.3. I²C START condition.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-3.png?nolink&300 |Figure 5.3. I²C START condition.}}
 //Figure 5.3. I²C START condition.// //Figure 5.3. I²C START condition.//
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-4.png?nolink&600 |Figure 5.4. I²C STOP condition.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-4.png?nolink&300 |Figure 5.4. I²C STOP condition.}}
 //Figure 5.4. I²C STOP condition.// //Figure 5.4. I²C STOP condition.//
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-5.png?nolink&600 |Figure 5.5. I²C data read/write sequence.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-5.png?nolink&300 |Figure 5.5. I²C data read/write sequence.}}
 //Figure 5.5. I²C data read/write sequence.// //Figure 5.5. I²C data read/write sequence.//
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-6.png?nolink&600 |Figure 5.6. I²C acknowledge sequence.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-5-6.png?nolink&300 |Figure 5.6. I²C acknowledge sequence.}}
 //Figure 5.6. I²C acknowledge sequence.// //Figure 5.6. I²C acknowledge sequence.//
  
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 //Figure 7.1. Picture of the MMA8652FC Accelerometer mounted on the Basys MX3 processor board.// //Figure 7.1. Picture of the MMA8652FC Accelerometer mounted on the Basys MX3 processor board.//
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-7-2.png?nolink&600 |Figure 7.2. Schematic diagram of MMA8652FC accelerator on the Basys MX3 processor board.}}+{{ :learn:courses:unit-4-lab4d:lab_4d_fig_7_2.jpg?nolink&700 |Figure 7.2. Schematic diagram of MMA8652FC accelerator on the Basys MX3 processor board.}}
 //Figure 7.2. Schematic diagram of MMA8652FC accelerator on the Basys MX3 processor board.// //Figure 7.2. Schematic diagram of MMA8652FC accelerator on the Basys MX3 processor board.//
 +
 +
  
 ==== 7.1. The MMZ8652FC 3-Axis Accelerometer Software ==== ==== 7.1. The MMZ8652FC 3-Axis Accelerometer Software ====
 The communications with the accelerometer requires two global functions that are made up of calls to the four hardware interface functions shown in Listings B.6 through B.9. The control flow diagrams for writing and reading a succession of accelerometer registers are shown in Fig. 7.3 and Fig. 7.4.  These two functions can only be called after the accelerometer has been initialized using the code in Listing B.5. The shaded blocks in Fig. 7.3 and Fig. 7.4 refer to coded functions provided in Listings B.2 through B.6. With the aid of the control flow diagrams shown in Fig. 7.3 and Fig. 7.4, the user is expected to develop their one i2cWriteBlk and i2cReradBlk functions. The communications with the accelerometer requires two global functions that are made up of calls to the four hardware interface functions shown in Listings B.6 through B.9. The control flow diagrams for writing and reading a succession of accelerometer registers are shown in Fig. 7.3 and Fig. 7.4.  These two functions can only be called after the accelerometer has been initialized using the code in Listing B.5. The shaded blocks in Fig. 7.3 and Fig. 7.4 refer to coded functions provided in Listings B.2 through B.6. With the aid of the control flow diagrams shown in Fig. 7.3 and Fig. 7.4, the user is expected to develop their one i2cWriteBlk and i2cReradBlk functions.
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-7-3.png?nolink&500 |Figure 7.3. Control Flow Diagram for writing a block of data to the MMA8652FC Accelerometer.}}+{{ :learn:courses:unit-4-lab4d:lab_4d_fig_7_3.jpg?nolink&200 |Figure 7.3. Control Flow Diagram for writing a block of data to the MMA8652FC Accelerometer.}}
 //Figure 7.3. Control Flow Diagram for writing a block of data to the MMA8652FC Accelerometer.// //Figure 7.3. Control Flow Diagram for writing a block of data to the MMA8652FC Accelerometer.//
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-7-4.png?nolink&500 |Figure 7.4. Control Flow Diagram for reading a block of data from the MMA8652FC Accelerometer.}}+{{ :learn:courses:unit-4-lab4d:lab_4d_fig_7_4.jpg?nolink&500 |Figure 7.4. Control Flow Diagram for reading a block of data from the MMA8652FC Accelerometer.}}
 //Figure 7.4. Control Flow Diagram for reading a block of data from the MMA8652FC Accelerometer.// //Figure 7.4. Control Flow Diagram for reading a block of data from the MMA8652FC Accelerometer.//
  
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 ===== 9. Questions ===== ===== 9. Questions =====
 1. Using the waveform captured in step 5 of the testing section, identify all portions of the I2C SDA and SCL signals starting with the START sequence and ending with the STOP sequence.\\ 1. Using the waveform captured in step 5 of the testing section, identify all portions of the I2C SDA and SCL signals starting with the START sequence and ending with the STOP sequence.\\
- 
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-9-1.png?nolink&600 |Figure 9.1. Screen capture showing the I2C timing for a 2-byte read operation.}} 
-//Figure 9.1. Screen capture showing the I2C timing for a 2-byte read operation.// 
- 
 2. Compute the effective data rate in bits per second.\\  2. Compute the effective data rate in bits per second.\\ 
 3. What effect, if any, would a change in the pull up resistors value for the SDA and SCL have on the I²C bus? \\ 3. What effect, if any, would a change in the pull up resistors value for the SDA and SCL have on the I²C bus? \\
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 ===== Appendix A: Unit 4 Parts Configuration ===== ===== Appendix A: Unit 4 Parts Configuration =====
-{{ :learn:courses:unit-4-lab4d:unit_4_-_photo_6.jpg?nolink&400 |Figure A.1. Unit 4 hardware and instrumentation configuration.}}+{{ :learn:courses:unit-4-lab4d:unit_4_-_photo_6.jpg?nolink&500 |Figure A.1. Unit 4 hardware and instrumentation configuration.}}
 //Figure A.1. Unit 4 hardware and instrumentation configuration.// //Figure A.1. Unit 4 hardware and instrumentation configuration.//
  
-{{ :learn:courses:unit-4-lab4d:lab4d-fig-a-2.png?nolink&400 |Figure A.2. PIC32MX I²C hardware block diagram.}}+{{ :learn:courses:unit-4-lab4d:lab4d-fig-a-2.png?nolink&600 |Figure A.2. PIC32MX I²C hardware block diagram.}}
 //Figure A.2. PIC32MX I²C hardware block diagram.// //Figure A.2. PIC32MX I²C hardware block diagram.//
  
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 } /* End of i2cReceiveOneByte */ } /* End of i2cReceiveOneByte */
 </code> </code>
 +
 +----
 +
 +[[{}/learn/courses/unit-4-1/start|Back to Unit 4 Part 1]]
 +[[{}/learn/courses/unit-4-2/start|Back to Unit 4 Part 2]]
 +[[{}/learn/courses/unit-4-lab4c/start|Back to Lab 4c]]
 +[[{}/learn/courses/unit-5/start|Go to Unit 5]]