Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| learn:courses:unit-4-lab4c:start [2017/03/29 21:43] – Martha | learn:courses:unit-4-lab4c:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
|---|---|---|---|
| Line 1: | Line 1: | ||
| ====== Lab 4c: Communications - SPI Serial Protocols ====== | ====== Lab 4c: Communications - SPI Serial Protocols ====== | ||
| + | [[{}/ | ||
| + | [[{}/ | ||
| + | [[{}/ | ||
| === Download This Document === | === Download This Document === | ||
| - | * {{ : | + | {{ : |
| ===== 1. Objectives ===== | ===== 1. Objectives ===== | ||
| - | | + | |
| - | | + | |
| - | | + | |
| Line 14: | Line 17: | ||
| ===== 2. Basic Knowledge ===== | ===== 2. Basic Knowledge ===== | ||
| - | | + | |
| - | | + | |
| - | | + | |
| Line 23: | Line 26: | ||
| ===== 3. Equipment List ===== | ===== 3. Equipment List ===== | ||
| ==== 3.1. Hardware ==== | ==== 3.1. Hardware ==== | ||
| - | | + | |
| - | | + | |
| - | | + | |
| In addition, we suggest the following instruments: | In addition, we suggest the following instruments: | ||
| - | | + | |
| ==== 3.2. Software ==== | ==== 3.2. Software ==== | ||
| The following programs must be installed on your development work station: | The following programs must be installed on your development work station: | ||
| - | | + | |
| - | | + | |
| - | | + | |
| - | | + | |
| - | | + | |
| ---- | ---- | ||
| ===== 4. Project Takeaways ===== | ===== 4. Project Takeaways ===== | ||
| - | | + | |
| - | | + | |
| - | | + | |
| ---- | ---- | ||
| Line 77: | Line 80: | ||
| When the microprocessor is connected to a slave device that has both input and output capability using SPI, as data is clocked out of the master, data is also clocked in from the slave device. This results in efficient data transfers for some slave devices. The loosely defined SPI interface requires careful consideration of the slave clock-data timing, as well as using a microprocessor that can be configured to support various timing requirements. Figure 5.3 shows the clock-data timing for the four SPI operating modes. The clock polarity (CPOL) controls the idle level of the SCK output from the master. If CPOL is high, then the idle level of SCK is high. The clock phase (CPHA) specifies when the data is to be changed or written to MOSI by the master and to MISO by the slave device. For example, when CPHA is low, the data signal (MISO for master and MOSI for the slave) is sampled by the receiving device when SCK makes a transition from the idle level to the active level. | When the microprocessor is connected to a slave device that has both input and output capability using SPI, as data is clocked out of the master, data is also clocked in from the slave device. This results in efficient data transfers for some slave devices. The loosely defined SPI interface requires careful consideration of the slave clock-data timing, as well as using a microprocessor that can be configured to support various timing requirements. Figure 5.3 shows the clock-data timing for the four SPI operating modes. The clock polarity (CPOL) controls the idle level of the SCK output from the master. If CPOL is high, then the idle level of SCK is high. The clock phase (CPHA) specifies when the data is to be changed or written to MOSI by the master and to MISO by the slave device. For example, when CPHA is low, the data signal (MISO for master and MOSI for the slave) is sampled by the receiving device when SCK makes a transition from the idle level to the active level. | ||
| - | {{ : | + | {{ : |
| //Figure 5.3. SPI timing modes.// | //Figure 5.3. SPI timing modes.// | ||
| + | |||
| Figure 5.4 shows the PIC32 settings for clock edge (CKE) and clock polarity (CKP). Table 5.1 provides the correlation between the conventional definitions of SPI mode CPHA and CPOL to those CKE and CKP settings. (Note: There is an apparent error in the Microchip table shown in Fig. 5.4. Both CKE and CKP should be equal to 1 for the fourth case of the SCK timing diagrams.) It is important to match the master processor operation to what the slave device is expecting. For some designs, it is possible for different slave devices to expect the master to operate in modes that are not the same. The PIC32 operating modes can be changed during program execution, but the modes should not be changed when the processor is actively clocking data on the SPI bus. | Figure 5.4 shows the PIC32 settings for clock edge (CKE) and clock polarity (CKP). Table 5.1 provides the correlation between the conventional definitions of SPI mode CPHA and CPOL to those CKE and CKP settings. (Note: There is an apparent error in the Microchip table shown in Fig. 5.4. Both CKE and CKP should be equal to 1 for the fourth case of the SCK timing diagrams.) It is important to match the master processor operation to what the slave device is expecting. For some designs, it is possible for different slave devices to expect the master to operate in modes that are not the same. The PIC32 operating modes can be changed during program execution, but the modes should not be changed when the processor is actively clocking data on the SPI bus. | ||
| Line 111: | Line 115: | ||
| Figure 7.1 shows the signal connections to the S25FL132K flash memory IC. Table 7.1 lists the PIC32MX370 processor pins that these signals are connected to. The PIC32 processor pin for the SPI_CE signal is configured as a digital output pin, as shown in Listing B.1. To implement the wiring configuration shown in Fig. 7.1, processor I/O pins PORT F:2 and PORTF:7 are mapped to SPI1T and SPI1R respectively using the first two statements in Listing B.2 in Appendix B. The PIC32MX370 PORTF:6 has a fixed assignment to SCK1. | Figure 7.1 shows the signal connections to the S25FL132K flash memory IC. Table 7.1 lists the PIC32MX370 processor pins that these signals are connected to. The PIC32 processor pin for the SPI_CE signal is configured as a digital output pin, as shown in Listing B.1. To implement the wiring configuration shown in Fig. 7.1, processor I/O pins PORT F:2 and PORTF:7 are mapped to SPI1T and SPI1R respectively using the first two statements in Listing B.2 in Appendix B. The PIC32MX370 PORTF:6 has a fixed assignment to SCK1. | ||
| - | {{ : | + | {{ : |
| //Figure 7.1. SPI flash memory IC schematic diagram.// | //Figure 7.1. SPI flash memory IC schematic diagram.// | ||
| Line 119: | Line 123: | ||
| | Chip Enable | | Chip Enable | ||
| | Serial Clock | SPI_SCK – 6 | PORT F Pin 6 – SCK1 | | | Serial Clock | SPI_SCK – 6 | PORT F Pin 6 – SCK1 | | ||
| - | | Flash Serial Input | SPI_SI – 5 | PORT F Pin 2 – SPI1R (MISO) | | + | | Flash Serial Input | SPI_SI – 5 | PORT F Pin 2 – SPI1R (MOSI) | |
| - | | Flash Serial Output | + | | Flash Serial Output |
| Line 126: | Line 130: | ||
| Using the SPI initialization shown in Listing B.2, the PIC32 processor is configured for SPI Mode 0 operation. Figure 7.2 shows that the bit output is held constant when the clock pulse makes a positive transition. Figure 7.2 also shows that the bit rate is 1 MHz. | Using the SPI initialization shown in Listing B.2, the PIC32 processor is configured for SPI Mode 0 operation. Figure 7.2 shows that the bit output is held constant when the clock pulse makes a positive transition. Figure 7.2 also shows that the bit rate is 1 MHz. | ||
| - | {{ : | + | {{ : |
| //Figure 7.2. SPI Bit timing for Mode 0 configuration.// | //Figure 7.2. SPI Bit timing for Mode 0 configuration.// | ||
| + | |||
| As Fig. A.2 shows, the same SPIxSR serial shift buffer is used for input and output, thus requiring the common SCKx clock signal. Hence, when a byte of data is shifted out of the SDOx pin, data is also being shifted into the SPIxSR from the SDIx pin. In other words, to receive SPI serial data, you must send SPI serial data. | As Fig. A.2 shows, the same SPIxSR serial shift buffer is used for input and output, thus requiring the common SCKx clock signal. Hence, when a byte of data is shifted out of the SDOx pin, data is also being shifted into the SPIxSR from the SDIx pin. In other words, to receive SPI serial data, you must send SPI serial data. | ||
| Line 156: | Line 161: | ||
| | Program Security Registers< | | Program Security Registers< | ||
| - | {{ : | + | {{ : |
| //Figure 7.3. Release Power Down/Read Device ID SPI transaction.// | //Figure 7.3. Release Power Down/Read Device ID SPI transaction.// | ||
| Line 203: | Line 208: | ||
| | Continuous Read Mode Reset< | | Continuous Read Mode Reset< | ||
| - | + | {{ : | |
| - | {{ : | + | |
| //Figure 7.4. SPI Flash Read Byte command and three-byte address followed by reading data ' | //Figure 7.4. SPI Flash Read Byte command and three-byte address followed by reading data ' | ||
| Line 296: | Line 300: | ||
| //Figure A.1. Unit 4 hardware and instrumentation configuration.// | //Figure A.1. Unit 4 hardware and instrumentation configuration.// | ||
| - | {{ : | ||
| - | //Figure A.2. SPI block diagram from the Microchip PIC32MX370 data sheet.// | ||
| ---- | ---- | ||
| Line 513: | Line 515: | ||
| </ | </ | ||
| + | ---- | ||
| + | |||
| + | [[{}/ | ||
| + | [[{}/ | ||
| + | [[{}/ | ||
| + | [[{}/ | ||
| + | [[{}/ | ||