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| learn:courses:unit-4-lab4c:start [2017/03/22 18:01] – [8.3. Construction Phase] Martha | learn:courses:unit-4-lab4c:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ====== Lab 4c: Communications - SPI Serial Protocols ====== | ====== Lab 4c: Communications - SPI Serial Protocols ====== | ||
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| === Download This Document === | === Download This Document === | ||
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| ===== 1. Objectives ===== | ===== 1. Objectives ===== | ||
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| ===== 2. Basic Knowledge ===== | ===== 2. Basic Knowledge ===== | ||
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| ===== 3. Equipment List ===== | ===== 3. Equipment List ===== | ||
| ==== 3.1. Hardware ==== | ==== 3.1. Hardware ==== | ||
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| In addition, we suggest the following instruments: | In addition, we suggest the following instruments: | ||
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| ==== 3.2. Software ==== | ==== 3.2. Software ==== | ||
| The following programs must be installed on your development work station: | The following programs must be installed on your development work station: | ||
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| ===== 4. Project Takeaways ===== | ===== 4. Project Takeaways ===== | ||
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| When the microprocessor is connected to a slave device that has both input and output capability using SPI, as data is clocked out of the master, data is also clocked in from the slave device. This results in efficient data transfers for some slave devices. The loosely defined SPI interface requires careful consideration of the slave clock-data timing, as well as using a microprocessor that can be configured to support various timing requirements. Figure 5.3 shows the clock-data timing for the four SPI operating modes. The clock polarity (CPOL) controls the idle level of the SCK output from the master. If CPOL is high, then the idle level of SCK is high. The clock phase (CPHA) specifies when the data is to be changed or written to MOSI by the master and to MISO by the slave device. For example, when CPHA is low, the data signal (MISO for master and MOSI for the slave) is sampled by the receiving device when SCK makes a transition from the idle level to the active level. | When the microprocessor is connected to a slave device that has both input and output capability using SPI, as data is clocked out of the master, data is also clocked in from the slave device. This results in efficient data transfers for some slave devices. The loosely defined SPI interface requires careful consideration of the slave clock-data timing, as well as using a microprocessor that can be configured to support various timing requirements. Figure 5.3 shows the clock-data timing for the four SPI operating modes. The clock polarity (CPOL) controls the idle level of the SCK output from the master. If CPOL is high, then the idle level of SCK is high. The clock phase (CPHA) specifies when the data is to be changed or written to MOSI by the master and to MISO by the slave device. For example, when CPHA is low, the data signal (MISO for master and MOSI for the slave) is sampled by the receiving device when SCK makes a transition from the idle level to the active level. | ||
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| //Figure 5.3. SPI timing modes.// | //Figure 5.3. SPI timing modes.// | ||
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| Figure 5.4 shows the PIC32 settings for clock edge (CKE) and clock polarity (CKP). Table 5.1 provides the correlation between the conventional definitions of SPI mode CPHA and CPOL to those CKE and CKP settings. (Note: There is an apparent error in the Microchip table shown in Fig. 5.4. Both CKE and CKP should be equal to 1 for the fourth case of the SCK timing diagrams.) It is important to match the master processor operation to what the slave device is expecting. For some designs, it is possible for different slave devices to expect the master to operate in modes that are not the same. The PIC32 operating modes can be changed during program execution, but the modes should not be changed when the processor is actively clocking data on the SPI bus. | Figure 5.4 shows the PIC32 settings for clock edge (CKE) and clock polarity (CKP). Table 5.1 provides the correlation between the conventional definitions of SPI mode CPHA and CPOL to those CKE and CKP settings. (Note: There is an apparent error in the Microchip table shown in Fig. 5.4. Both CKE and CKP should be equal to 1 for the fourth case of the SCK timing diagrams.) It is important to match the master processor operation to what the slave device is expecting. For some designs, it is possible for different slave devices to expect the master to operate in modes that are not the same. The PIC32 operating modes can be changed during program execution, but the modes should not be changed when the processor is actively clocking data on the SPI bus. | ||
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| ===== 7. Background Information ===== | ===== 7. Background Information ===== | ||
| ==== 7.1. PIC32MX370 SPI I/O ==== | ==== 7.1. PIC32MX370 SPI I/O ==== | ||
| - | Figure 7.1 shows the signal connections to the S25FL132K flash memory IC. Table 7.1 lists the PIC32MX370 processor pins that these signals are connected to. The PIC32 processor pin for the SPI_CE signal is configured as a digital output pin. To implement the wiring configuration shown in Fig. 7.1, processor I/O pins PORT F:2 and PORTF:7 are mapped to SPI1T and SPI1R respectively using the first two statements in Listing B.1 in Appendix B. The PIC32MX370 PORTF:6 has a fixed assignment to SCK1. | + | Figure 7.1 shows the signal connections to the S25FL132K flash memory IC. Table 7.1 lists the PIC32MX370 processor pins that these signals are connected to. The PIC32 processor pin for the SPI_CE signal is configured as a digital output pin, as shown in Listing B.1. To implement the wiring configuration shown in Fig. 7.1, processor I/O pins PORT F:2 and PORTF:7 are mapped to SPI1T and SPI1R respectively using the first two statements in Listing B.2 in Appendix B. The PIC32MX370 PORTF:6 has a fixed assignment to SCK1. |
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| //Figure 7.1. SPI flash memory IC schematic diagram.// | //Figure 7.1. SPI flash memory IC schematic diagram.// | ||
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| | Chip Enable | | Chip Enable | ||
| | Serial Clock | SPI_SCK – 6 | PORT F Pin 6 – SCK1 | | | Serial Clock | SPI_SCK – 6 | PORT F Pin 6 – SCK1 | | ||
| - | | Flash Serial Input | SPI_SI – 5 | PORT F Pin 2 – SPI1R (MISO) | | + | | Flash Serial Input | SPI_SI – 5 | PORT F Pin 2 – SPI1R (MOSI) | |
| - | | Flash Serial Output | + | | Flash Serial Output |
| ==== 7.2. Interface with SPI Flash Memory ==== | ==== 7.2. Interface with SPI Flash Memory ==== | ||
| - | Using the SPI initialization shown in Listing | + | Using the SPI initialization shown in Listing |
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| //Figure 7.2. SPI Bit timing for Mode 0 configuration.// | //Figure 7.2. SPI Bit timing for Mode 0 configuration.// | ||
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| As Fig. A.2 shows, the same SPIxSR serial shift buffer is used for input and output, thus requiring the common SCKx clock signal. Hence, when a byte of data is shifted out of the SDOx pin, data is also being shifted into the SPIxSR from the SDIx pin. In other words, to receive SPI serial data, you must send SPI serial data. | As Fig. A.2 shows, the same SPIxSR serial shift buffer is used for input and output, thus requiring the common SCKx clock signal. Hence, when a byte of data is shifted out of the SDOx pin, data is also being shifted into the SPIxSR from the SDIx pin. In other words, to receive SPI serial data, you must send SPI serial data. | ||
| - | Listing B.2 shows the function that can be used to send, receive, or exchange a byte of data using SPI communications. In most cases, when the SPI master is sending header data to the slave, the master SPI ignores the data received on the SDIx pin. Similarly, as the master continues to send non-consequential data during a SPI slave read operation, the slave SPI discards the data sent to it. The SPI master clock must be generated for both sending and receiving. | + | Listing B.3 shows the function that can be used to send, receive, or exchange a byte of data using SPI communications. In most cases, when the SPI master is sending header data to the slave, the master SPI ignores the data received on the SDIx pin. Similarly, as the master continues to send non-consequential data during a SPI slave read operation, the slave SPI discards the data sent to it. The SPI master clock must be generated for both sending and receiving. |
| === 7.2.1. SPI Flash Memory Software === | === 7.2.1. SPI Flash Memory Software === | ||
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| | Program Security Registers< | | Program Security Registers< | ||
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| //Figure 7.3. Release Power Down/Read Device ID SPI transaction.// | //Figure 7.3. Release Power Down/Read Device ID SPI transaction.// | ||
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| | Continuous Read Mode Reset< | | Continuous Read Mode Reset< | ||
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| //Figure 7.4. SPI Flash Read Byte command and three-byte address followed by reading data ' | //Figure 7.4. SPI Flash Read Byte command and three-byte address followed by reading data ' | ||
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| - Download the completed functional project to the PIC32MX370 processor and test by running the project. | - Download the completed functional project to the PIC32MX370 processor and test by running the project. | ||
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| //Figure 8.1. Call map for SPI FLash Write Page.// | //Figure 8.1. Call map for SPI FLash Write Page.// | ||
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| //Figure 8.2. Call map for SPI Flash Erase.// | //Figure 8.2. Call map for SPI Flash Erase.// | ||
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| ==== 8.5. SPI Design Challenge ==== | ==== 8.5. SPI Design Challenge ==== | ||
| - | Replace the code in Listing B.6 for the function “SPIFLASH_WritePage” that uses software-intensive “for” loops with one that uses DMA. | + | Replace the code in Listing B.7 for the function “SPIFLASH_WritePage” that uses software-intensive “for” loops with one that uses DMA. |
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| ===== 9. Questions ===== | ===== 9. Questions ===== | ||
| - | 1. Whyy does SPI normally have higher data transfer rates?\\ | + | 1. Why does SPI normally have higher data transfer rates?\\ |
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| - | - No overhead to select the slave device.\\ | + | |
| - | - Full-duplex operation\\ | + | |
| - | - Higher maximum SCK speeds\\ | + | |
| - | - No ACK bit for each 8 data bits\\ | + | |
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| 2. Is it necessary for the SPI SCK signal to have a 50% duty cycle?\\ | 2. Is it necessary for the SPI SCK signal to have a 50% duty cycle?\\ | ||
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| - | No. However, the minimum duty cycle is constrained to be greater than the period of 2 times the maximum SPI clock rate.\\ | ||
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| 3. Can text data be sent using SPI communications? | 3. Can text data be sent using SPI communications? | ||
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| 4. Can SPI master be configured for only receiving data without transmitting data?\\ | 4. Can SPI master be configured for only receiving data without transmitting data?\\ | ||
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| - | No. The only way to generate a clock is by sending data. The MOSI pin will send useless data that will be ignored by devices on the SPI MOSI bus that are not selected by a chip enable. | ||
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| 5. How many slave devices can be connected to the SPI bus?\\ | 5. How many slave devices can be connected to the SPI bus?\\ | ||
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| - | This question does not have a simple answer. It depends on the pin capacitance and input current leakage of the slave devices, the clock speed, and the physical length of the bus wires. The bigger issue is probably the number of processor pins that are available for the device select.</ | ||
| 6. What will happen to the SPI communications is an interrupt occurs in the middle of a transmission? | 6. What will happen to the SPI communications is an interrupt occurs in the middle of a transmission? | ||
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| - | Nothing. It is the clock edges that causes the data on the MISO and MOSI bus to be sensed. The clock pulses can be stretched without consequences. See question 2. | ||
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| //Figure A.1. Unit 4 hardware and instrumentation configuration.// | //Figure A.1. Unit 4 hardware and instrumentation configuration.// | ||
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| - | //Figure A.2. SPI block diagram from the Microchip PIC32MX370 data sheet.// | ||
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| ===== Appendix B: Allocating a Heap in MPLAB X ===== | ===== Appendix B: Allocating a Heap in MPLAB X ===== | ||
| - | ==== Listing B.1. SPI Channel 1 Initialization for Master Mode ==== | + | ==== Listing B.1. Flash Memory SPI Initialization ==== |
| + | < | ||
| + | #define SPIFLASH_SEL | ||
| + | #define SPIFLASH_CS_TRIS | ||
| + | unsigned int flash_mem_init(void) | ||
| + | { | ||
| + | unsigned int bitrate; | ||
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| + | bitrate = init_SPI1(); | ||
| + | SPIFLASH_CS_TRIS = 0; // Set FLASH select as output | ||
| + | SPIFLASH_SEL = 1; // Reset FLASH chip select | ||
| + | return bitrate; | ||
| + | } | ||
| + | </ | ||
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| + | ==== Listing B.2. SPI Channel 1 Initialization for Master Mode ==== | ||
| < | < | ||
| #define MAX_SPI_CLK_FREQ | #define MAX_SPI_CLK_FREQ | ||
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| </ | </ | ||
| - | ==== Listing B.2. SPI Channel 1 Byte Transaction ==== | + | ==== Listing B.3. SPI Channel 1 Byte Transaction ==== |
| < | < | ||
| BYTE spiXfer(BYTE data_out) | BYTE spiXfer(BYTE data_out) | ||
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| </ | </ | ||
| - | ==== Listing B.3. FLASH Transfer Bytes ==== | + | ==== Listing B.4. FLASH Transfer Bytes ==== |
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| void SPIFLASH_TrasferBytes(int nBytes, unsigned char *pbRdData, | void SPIFLASH_TrasferBytes(int nBytes, unsigned char *pbRdData, | ||
| unsigned char *pbWrData) | unsigned char *pbWrData) | ||
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| </ | </ | ||
| - | ==== Listing B.4. FLASH Release Power Down and Read Device ID === | + | ==== Listing B.5. FLASH Release Power Down and Read Device ID === |
| < | < | ||
| void SPIFLASH_ReleasePowerDownGetDeviceID(BYTE *rd) | void SPIFLASH_ReleasePowerDownGetDeviceID(BYTE *rd) | ||
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| </ | </ | ||
| - | ==== Listing B.5. SPI Write Data to Flash ==== | + | ==== Listing B.6. SPI Write Data to Flash ==== |
| < | < | ||
| int SPIFLASH_WriteData(int nBytes, BYTE *pbWrData, unsigned int flashAddr) | int SPIFLASH_WriteData(int nBytes, BYTE *pbWrData, unsigned int flashAddr) | ||
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| </ | </ | ||
| - | ==== Listing B.6. SPI Write Page Data to Flash ==== | + | ==== Listing B.7. SPI Write Page Data to Flash ==== |
| < | < | ||
| static int SPIFLASH_WritePage(int nBytes, unsigned char *pbWrData, | static int SPIFLASH_WritePage(int nBytes, unsigned char *pbWrData, | ||
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| </ | </ | ||
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