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| learn:courses:unit-3:start [2017/02/13 21:44] – [Unit 3: Parallel IO and Handshaking for LCD Control] Martha | learn:courses:unit-3:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| - | ====== Unit 3: Parallel | + | ====== Unit 3: Parallel |
| - | -->Unit 3 Labs# | + | [[: |
| - | * [[https:// | + | === Unit 3 Labs === |
| - | * [[https:// | + | * [[/ |
| + | * [[/ | ||
| - | <-- | + | === Download This Document |
| - | + | {{ : | |
| - | == Download This Document == | + | |
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| ===== 1. Introduction ===== | ===== 1. Introduction ===== | ||
| - | In this lab, you will learn how to interface a PIC32 processor to a character liquid crystal display (LCD) using 8-bit parallel data lines and handshaking using bit-banging techniques. You will learn to translate timing diagrams provided by target equipment data sheets into timed sequences of program instructions. You will also learn how to use ASCII encoded data and control to generate a stable and easily readable display of real-time data. | + | Throughout Unit 3 and Labs [[/ |
| You will experiment with the mechanisms required to synchronize asynchronous systems using hardware and software handshaking, | You will experiment with the mechanisms required to synchronize asynchronous systems using hardware and software handshaking, | ||
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| - Identify the PIC32 processor pins used for the LCD interface. | - Identify the PIC32 processor pins used for the LCD interface. | ||
| - Write a library of functions, providing the general capability to display strings of text, characters, and numbers at specified positions on the LCD display. All of these functions have strict timing requirements. | - Write a library of functions, providing the general capability to display strings of text, characters, and numbers at specified positions on the LCD display. All of these functions have strict timing requirements. | ||
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| - Display static and dynamic text on the LCD. | - Display static and dynamic text on the LCD. | ||
| - Verify that the timing of the handshaking meets the specified minimums. | - Verify that the timing of the handshaking meets the specified minimums. | ||
| - Understand handshaking requirements for interfacing two systems operating at differing clock speeds. | - Understand handshaking requirements for interfacing two systems operating at differing clock speeds. | ||
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| ===== 4. Unit Equipment List ===== | ===== 4. Unit Equipment List ===== | ||
| ==== 4.1. Hardware ==== | ==== 4.1. Hardware ==== | ||
| - | - PC or Linux Workstation computer. | + | - [[https:// |
| - | | + | * The 2X16 LCD included on the Basys MX3 processor board can display 16 characters on each of its two lines. The display can be more easily viewed if the LCD backlight is switched on using the slide switch SW9. |
| - | - [[http://store.digilentinc.com/ | + | - [[https://digilent.com/shop/ |
| - | - [[http://store.digilentinc.com/ | + | - Workstation computer running Windows 10 or higher, MAC OS, or Linux |
| - | | + | |
| + | In addition, we suggest the following instruments: | ||
| + | - [[https://digilent.com/shop/ | ||
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| ==== 4.2. Software ==== | ==== 4.2. Software ==== | ||
| - | | + | The following programs must be installed on your development work station: |
| - | - [[http:// | + | |
| - | - [[http://store.digilentinc.com/waveforms-2015-download-only/ | + | - [[http:// |
| + | - [[http://www.microchip.com/xcdemo/ | ||
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| ===== 5. Project Takeaways ===== | ===== 5. Project Takeaways ===== | ||
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| ===== 6. Fundamental Concepts ===== | ===== 6. Fundamental Concepts ===== | ||
| ==== 6.1. Communications ==== | ==== 6.1. Communications ==== | ||
| - | Digital communication is an electronic transfer of information between two electronic devices. Parallel communication is a method of conveying multiple binary data bits simultaneously. It contrasts with [[https:// | + | Digital communication is an electronic transfer of information between two electronic devices. |
| - | ==== 6.2. Handshaking: | + | ---- |
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| + | ===== 7. Background Information ===== | ||
| + | ==== 7.1. Handshaking: | ||
| [[https:// | [[https:// | ||
| - | The exact implementation of the handshaking process comes in many forms, but it may be classified as either explicit or implicit. Explicit handshaking uses dedicated hardware control signals to indicate the impending action from the sender and readiness of the receiving device, as shown in Fig. 6.1. Each of the two handshaking signals has two possible states. The basic concepts are that the receiving device must indicate when it is ready to receive data and when it is done. The sending device must tell the receiving device when new data is ready and when the data is no longer available. | + | The exact implementation of the handshaking process comes in many forms, but it may be classified as either explicit or implicit. Explicit handshaking uses dedicated hardware control signals to indicate the impending action from the sender and readiness of the receiving device, as shown in Fig. 7.1. Each of the two handshaking signals has two possible states. The basic concepts are that the receiving device must indicate when it is ready to receive data and when it is done. The sending device must tell the receiving device when new data is ready and when the data is no longer available. |
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| - | The timing diagram shown in Fig. 6.2 illustrates the sequence of events required for the sender to transfer data to the receiver using a four-phase handshaking protocol. The shaded area on the data signal indicates intervals when the data level is permitted to change from high to low or low to high. At time “A,” the receiver asserts the RxRdy signal high to indicate to the sender that it is ready to accept data. When the sender has information to send to the receiver, it first asserts the data signals high or low (indicated at time “B”) and then asserts the TxReq signal high at time “C” to indicate the data is now available to be read. The time interval between “B” and “C” is called the data setup time and is specified by the receiving device. At some point in the interval between times “C” and “D”, the receiving device reads the data bus. The receiving device then asserts the RxRdy signal low to indicate to the sender that it has acquired the data. The sending device then asserts its TxReq signal low at time “E” to indicate to the receiver that the data is no longer available on the data bus. The data must not actually change until time “F” to meet the data hold time specified by the receiving device. The minimum time between successive time points marked “A” is called the cycle time. Regardless of how quickly the sender is able to send data, the data maximum exchange rate must conform to the specifications of the receiving device. | + | The timing diagram shown in Fig. 7.2 illustrates the sequence of events required for the sender to transfer data to the receiver using a four-phase handshaking protocol. The shaded area on the data signal indicates intervals when the data level is permitted to change from high to low or low to high. At time “A,” the receiver asserts the RxRdy signal high to indicate to the sender that it is ready to accept data. When the sender has information to send to the receiver, it first asserts the data signals high or low (indicated at time “B”) and then asserts the TxReq signal high at time “C” to indicate the data is now available to be read. The time interval between “B” and “C” is called the data setup time and is specified by the receiving device. At some point in the interval between times “C” and “D”, the receiving device reads the data bus. The receiving device then asserts the RxRdy signal low to indicate to the sender that it has acquired the data. The sending device then asserts its TxReq signal low at time “E” to indicate to the receiver that the data is no longer available on the data bus. The data must not actually change until time “F” to meet the data hold time specified by the receiving device. The minimum time between successive time points marked “A” is called the cycle time. Regardless of how quickly the sender is able to send data, the data maximum exchange rate must conform to the specifications of the receiving device. |
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| - | For bidirectional data exchanges, the handshaking signal must be mirrored, as illustrated in Fig. 6.3. Data sent in only one direction (as illustrated in Fig. 6.1) is called [[http:// | + | For bidirectional data exchanges, the handshaking signal must be mirrored, as illustrated in Fig. 7.3. Data sent in only one direction (as illustrated in Fig. 7.1) is called [[http:// |
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| - | A four-phase handshaking scheme can use an explicit strobe signal from the sender to the receiver and implicit handshaking from the receiver to the sender. The sender assumes implicitly that the receiver is ready, provided the timing constraints for the receiving device are met. Figures | + | A four-phase handshaking scheme can use an explicit strobe signal from the sender to the receiver and implicit handshaking from the receiver to the sender. The sender assumes implicitly that the receiver is ready, provided the timing constraints for the receiving device are met. Figures |
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| There is also a two-phase handshaking scheme that is beyond the scope of this discussion. The interested reader should refer to the web link at [[http:// | There is also a two-phase handshaking scheme that is beyond the scope of this discussion. The interested reader should refer to the web link at [[http:// | ||
| - | ==== 6.3. LCD Hardware Interface ==== | + | ==== 7.2. LCD Hardware Interface ==== |
| - | We are using an LCD with a parallel interface to demonstrate the concept of handshaking needed for electronic communications. The LCD will be used in many of the future projects to serve as a local display of varying data. The general hardware configuration for this project is shown in Fig. A.1 of Appendix A. The Basys MX3 processor board shows that it is populated with an SD1602GSLB LCD for which the datasheet is incomplete. It includes the correct pinout, which we have listed here in Table 6.1; however, it does not include the necessary timing requirements. Because the SC1602B model uses the same Samsung KS0066 controller, we will assume it is sufficiently similar and use the timing information from the SC1602B datasheet. | + | We are using an LCD with a parallel interface to demonstrate the concept of handshaking needed for electronic communications. The LCD will be used in many of the future projects to serve as a local display of varying data. The general hardware configuration for this project is shown in Fig. A.1 of Appendix A. The Basys MX3 processor board shows that it is populated with an SD1602GSLB LCD (for which the datasheet is incomplete). It includes the correct pinout, which we have listed here in Table 7.1; however, it does not include the necessary timing requirements. Because the SC1602B model uses the same Samsung KS0066 controller |
| - | **Table | + | **Table |
| ^ Port # ^ Processor Function | ^ Port # ^ Processor Function | ||
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| Although LCD units produced by various manufacturers have different numbers of characters per line and different numbers of display lines, they have an interface that has become a de facto standard. This interface will be discussed in detail in the following paragraphs. | Although LCD units produced by various manufacturers have different numbers of characters per line and different numbers of display lines, they have an interface that has become a de facto standard. This interface will be discussed in detail in the following paragraphs. | ||
| - | There are three signals that the microprocessor uses to control the data transfer with the LCD module. The Enable (E) signal is a read or write strobe, depending on whether the Read/!Write signal is high or low. (The “!” character indicates that the signal is active when the signal is asserted low, commonly referred to as “active low.”) The action of the read and write operations | + | There are three signals that the microprocessor uses to control the data transfer with the LCD module. The Enable (E) signal is a read or write strobe, depending on whether the Read/!Write signal is high or low. (The “!” character indicates that the signal is active when the signal is asserted low, commonly referred to as “active low.”) The action of the read and write operations |
| - | The hardware configuration | + | Figure 7.8 shows the timing diagram for the LCD write cycle. |
| - | Figure 6.8 shows the timing diagram for the LCD write cycle. The RS and the R/W signals must be asserted for a period equal to or longer than the time specified by the RS and R/W setup time parameter, t< | + | The processor must assert the E signal high for a minimum time as specified by the period, t< |
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| - | The processor must assert the E signal high for a minimum time as specified by the period, t< | + | |
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| - | The LCD read cycle timing provided in Fig. 6.9 shows that both the RS and R/W signals must be asserted for a period equal to or longer than the time specified by the R/W setup time parameter, t< | + | The LCD read cycle timing provided in Fig. 7.9 shows that both the RS and R/W signals must be asserted for a period equal to or longer than the time specified by the R/W setup time parameter, t< |
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| - | The minimum time before the read or write operation can be repeated is set by the enable cycle time, t< | + | The minimum time before the read or write operation can be repeated is set by the enable cycle time, t< |
| - | **Table | + | **Table |
| ^ Mode ^ Characteristic | ^ Mode ^ Characteristic | ||
| | Write Mode\\ Refer to Figure 6.8 | E Cycle Time | t< | | Write Mode\\ Refer to Figure 6.8 | E Cycle Time | t< | ||
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| | ::: | Data Hold Time | t< | | ::: | Data Hold Time | t< | ||
| - | ==== 6.4. LCD Software Interface ==== | + | ==== 7.3. LCD Software Interface ==== |
| - | The character LCD has an initialization or configuration phase before the operational phase. One approach to software development for this project is to partition the software into six functions or modules, as shown in Fig. 6.10. Detailed control flow diagrams for the LCD Write and the LCD Read functions are provided by Fig. 6.12 and Fig. 6.13. The control flow diagrams only apply for code that uses bit-banging techniques for implementing the LCD interface, as discussed in detail below. These LCD read and write functions control the hardware interface and must be specifically written to match the I/O pin connections from the microprocessor to the LCD unit. The remaining four LCD functional blocks depicted in Fig. 6.10 are not dependent on hardware connections. | + | The character LCD has an initialization or configuration phase before the operational phase. One approach to software development for this project is to partition the software into six functions or modules, as shown in Fig. 7.10. Detailed control flow diagrams for the LCD Write and the LCD Read functions are provided by Fig. 7.12 and Fig. 7.13. The control flow diagrams only apply for code that uses bit-banging techniques for implementing the LCD interface, as discussed in detail below. These LCD read and write functions control the hardware interface and must be specifically written to match the I/O pin connections from the microprocessor to the LCD unit. The remaining four LCD functional blocks depicted in Fig. 7.10 are not dependent on hardware connections. |
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| - | The LCD configuration sequence is a series of commands written to the LCD after a power-up or CPU reset. The values that are written to the LCD, shown in Fig. 6.11, set up the LCD for an 8-bit data interface with a blinking cursor. The cursor address is reset to zero, placing the cursor at the start of the first line. The cursor address automatically increments as new DDRAM __data__ | + | The LCD configuration sequence is a series of commands written to the LCD after a power-up or CPU reset. The values that are written to the LCD, shown in Fig. 7.11, set up the LCD for an 8-bit data interface with a blinking cursor. The cursor address is reset to zero, placing the cursor at the start of the first line. The cursor address automatically increments as new DDRAM data is written to the LCD. The cursor address is the memory address of the DDRAM where the cursor is seen and the location where the next character written to the DDRAM will be displayed. Note that the Busy Flag is not polled during the initialization because it may not be valid until the sequence is completed. |
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| - | Due to the high execution speed of the PIC32 processor, the “Wait” tasks shown in Fig. 6.12 and Fig. 6.13 are required to be implemented as software delays. The LCD Write and LCD Read software flow diagrams represent the transfer of data from the PIC32 to one of two internal LCD registers. The internal operations of the LCD operate at a much slower speed, as shown in Fig. 6.14. It should be noted that the busy flag will be read immediately following the writing of an instruction. The next instruction, | + | Due to the high execution speed of the PIC32 processor, the “Wait” tasks shown in Fig. 7.12 and Fig. 7.13 are required to be implemented as software delays. The LCD Write and LCD Read software flow diagrams represent the transfer of data from the PIC32 to one of two internal LCD registers. The internal operations of the LCD operate at a much slower speed, as shown in Table 7.3. It should be noted that the busy flag will be read immediately following the writing of an instruction. The next instruction, |
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| - | The LCD has an additional set of buffer registers labeled the IR and DR. The PIC32 can write to these two registers following the timing requirements shown in Table 6.2, or following the control flow diagrams shown in Fig. 6.12 and Fig. 6.13; however, the LCD has a much slower clock speed and requires more time to implement the instructions written to the buffer. The actual LCD minimum implementation times are shown in Fig. 6.14. One method of incorporating the various implementation times is to add time delay after the instruction has been written. Doing so requires that the additional delay be over specified to ensure proper LCD operation. | + | The LCD has an additional set of buffer registers labeled the IR and DR. The PIC32 can write to these two registers following the timing requirements shown in Table 7.2, or following the control flow diagrams shown in Fig. 7.12 and Fig. 7.13; however, the LCD has a much slower clock speed and requires more time to implement the instructions written to the buffer. The actual LCD minimum implementation times are shown in Table 7.3. One method of incorporating the various implementation times is to add time delay after the instruction has been written. Doing so requires that the additional delay be over specified to ensure proper LCD operation. |
| - | {{ :learn:courses:unit-3:figure-6-14.png? | + | **Table 7.3. LCD control instruction tables.** |
| - | //Figure 6.14. LCD control instruction tables.// | + | ^ Instruction |
| + | | ::: ^ RS ^ R/W ^ DB7 ^ DB6 ^ DB5 ^ DB4 ^ DB3 ^ DB2 ^ DB1 ^ DB0 | ::: | ::: | | ||
| + | | Clear Display | ||
| + | | Return Home | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | - | Set DDRAM address to " | ||
| + | | Entry Mode Set | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | I/D | SH | Assign cursor moving direction and enable the shift of entire display. | 39 μs | | ||
| + | | Display ON/OFF Control | ||
| + | | Cursor or Display Shift | 0 | 0 | 0 | 0 | 0 | 1 | S/C | R/L | - | - | Set cursor moving and display shift control bit, and the direction, without changing of DDRAM data. | 39 μs | | ||
| + | | Function Set | 0 | 0 | 0 | 0 | 1 | DL | N | F | - | - | Set interface data length (DL: 8-bit/ | ||
| + | | Set CGRAM Address | ||
| + | | Set DDRAM Address | ||
| + | | Read Busy Flag and Address | ||
| + | | Write Data to RAM | 1 | 0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Write data into internal RAM (DDRAM/CGRAM). | ||
| + | | Read Data from RAM | 1 | 1 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | Read data from internal RAM (DDRAM/CGRAM). | ||
| As described above, the LCD controller has two sets of memory registers: one for configuring the LCD operations and one for holding the data that generates the LCD display characters. The register select (RS) signal controls which set of memory registers are accessed for both read and write operations. The display memory is further divided into memory for the display of a fixed set of symbols and characters and memory that can be used to generate user defined characters. The display data Ram (DDRAM) is used for displaying the [[http:// | As described above, the LCD controller has two sets of memory registers: one for configuring the LCD operations and one for holding the data that generates the LCD display characters. The register select (RS) signal controls which set of memory registers are accessed for both read and write operations. The display memory is further divided into memory for the display of a fixed set of symbols and characters and memory that can be used to generate user defined characters. The display data Ram (DDRAM) is used for displaying the [[http:// | ||
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| The character generator RAM (CGRAM) is used to generate special symbols that can be programmed by the controlling processor. Accessing the CGRAM and generating special LCD symbols and characters is beyond the scope of this project. See Appendix C for information regarding configuring the LCD for this mode of operation. | The character generator RAM (CGRAM) is used to generate special symbols that can be programmed by the controlling processor. Accessing the CGRAM and generating special LCD symbols and characters is beyond the scope of this project. See Appendix C for information regarding configuring the LCD for this mode of operation. | ||
| - | Other than the LCD initialization function, the LCD Write and Read functions depicted in Fig. 6.12 and Fig. 6.13 are the only functions that directly interface to the LCD hardware. The same LCD byte write function is used whenever sending a byte to either the data RAM or to the control registers. This is possible because the value that RS is to be set to is passed to the LCD read and LCD write functions. The advantage of implementing the LCD control in this manner is that it limits the hardware specific code to these two functions. This maximizes the portability of user code to different applications, | + | Other than the LCD initialization function, the LCD Write and Read functions depicted in Fig. 7.12 and Fig. 7.13 are the only functions that directly interface to the LCD hardware. The same LCD byte write function is used whenever sending a byte to either the data RAM or to the control registers. This is possible because the value that RS is to be set to is passed to the LCD read and LCD write functions. The advantage of implementing the LCD control in this manner is that it limits the hardware specific code to these two functions. This maximizes the portability of user code to different applications, |
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| After initializing, | After initializing, | ||
| - | Figure | + | Figure |
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| - | After reading the cursor address and busy flag, the next step shown in Fig. 6.15 requires testing the binary value of the character passed to this function to determine if it is an ASCII control character. For instance, when either the [[http:// | + | After reading the cursor address and busy flag, the next step shown in Fig. 7.14 requires testing the binary value of the character passed to this function to determine if it is an ASCII control character. For instance, when either the [[http:// |
| - | If writing a string of ASCII text to the LCD, the cursor address is automatically incremented to point to the next character position. No characters will be displayed if the cursor address is between 0x10 and 0x3F, hence the cursor does not automatically increment from the end of the first line to the beginning of the second line. It requires additional code to reposition the cursor from the end of the first line to beginning of the second. This is accomplished by writing the new cursor address, 0x40, added to the write DDRAM control bit, 0x80, resulting in a value of 0xC0 that is written to the LCD with the RS and RW signals set low. At this point, the program must wait until the busy flag is set to zero before continuing on with the process of writing the next character to the LCD. The busy flag represents a blocking [[http:// | + | If writing a string of ASCII text to the LCD, the cursor address is automatically incremented to point to the next character position. No characters will be displayed if the cursor address is between 0x10 and 0x3F, hence the cursor does not automatically increment from the end of the first line to the beginning of the second line. It requires additional code to reposition the cursor from the end of the first line to beginning of the second. This is accomplished by writing the new cursor address, 0x40, added to the write DDRAM control bit, 0x80, resulting in a value of 0xC0 that is written to the LCD with the RS and RW signals set low. At this point, the program must wait until the busy flag is set to zero before continuing on with the process of writing the next character to the LCD. The busy flag represents a blocking [[http:// |
| - | Most LCD modules require multiple microseconds to complete the CLEAR DISPLAY and RETURN HOME commands. According to the Samsung KS006U data sheet, operations other than READ BUSY FLAG and ADDRESS, CLEAR DISPLAY, and RETURN HOME operations can require up to 43 μs to complete. The CLEAR DISPLAY and RETURN HOME operations can require up to 1.53 ms to complete. The READ BUSY FLAG and ADDRESS operation can be completed as quickly as the LCD timing permits. This allows LCD BUSY FLAG to be polled at the maximum rate provided by the minimum Enable cycle time shown in Fig. 6.8 and Fig. 6.9. The time to complete any write operation varies from one LCD manufacturer to another, so the particular device data sheet must be examined closely. The Enable cycle time parameter, t< | + | Most LCD modules require multiple microseconds to complete the CLEAR DISPLAY and RETURN HOME commands. According to the [[http:// |
| - | ==== 6.5. Bit-banging LCD Interface ==== | + | ==== 7.3. Bit-banging LCD Interface ==== |
| - | Any microprocessor can interface to a character LCD using the technique called “[[http:// | + | Any microprocessor can interface to a character LCD using the technique called “[[http:// |
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| - | ==== Listing | + | ==== Listing |
| < | < | ||
| #include < | #include < | ||
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| - | ==== 6.6. Parallel Master Port LCD Interface ==== | + | ==== 7.5. Parallel Master Port LCD Interface ==== |
| The PIC32 family of processors is enabled with an addressable parallel port called the Parallel Master Port, or PMP. The Basys MX3 trainer board was designed to take advantage of this resource when interfacing with the onboard parallel interface LCD. Using the PMP interface to the LCD is an alternative method to the bit-banging approach described above. It is beyond the scope of this project to explain all of the various ways the PMP can be configured. In general, the PMP consists of an 8- or 16-bit bidirectional parallel I/O data bus, a dedicated or multiplexed address bus, and control signals to allow read, write, and address latch enable operations. | The PIC32 family of processors is enabled with an addressable parallel port called the Parallel Master Port, or PMP. The Basys MX3 trainer board was designed to take advantage of this resource when interfacing with the onboard parallel interface LCD. Using the PMP interface to the LCD is an alternative method to the bit-banging approach described above. It is beyond the scope of this project to explain all of the various ways the PMP can be configured. In general, the PMP consists of an 8- or 16-bit bidirectional parallel I/O data bus, a dedicated or multiplexed address bus, and control signals to allow read, write, and address latch enable operations. | ||
| - | The purpose of the PMP is to facilitate a single parallel data bus interface with multiple devices. The general architecture of a parallel data bus is shown in Fig. 6.18. Figure | + | The purpose of the PMP is to facilitate a single parallel data bus interface with multiple devices. The general architecture of a parallel data bus is shown in Fig. 7.15. Figure |
| - | The address bus is configured as a 1-bit signal representing address signal A0 connected to the LCD RS input. The PIC32 strobe output pin is connected to the LCD E input and the PIC32 read/write output control pin to the LCD R/W input. The PIC32 pins assigned to the PMP functions are fixed in hardware. The Basys MX3 interface with the LCD uses the PMP pin assignment shown in Fig. 6.16. | + | The address bus is configured as a 1-bit signal representing address signal A0 connected to the LCD RS input. The PIC32 strobe output pin is connected to the LCD E input and the PIC32 read/write output control pin to the LCD R/W input. The PIC32 pins assigned to the PMP functions are fixed in hardware. The Basys MX3 interface with the LCD uses the PMP pin assignment shown in Fig. 7.16. |
| - | {{ : | ||
| - | //Figure 6.16. Architecture of a parallel data bus.// | ||
| - | {{ : | + | {{ : |
| - | // | + | // |
| - | Since the some of the pins used for the LCD interface with the PIC32MX370 processor are either analog inputs or digital | + | {{ : |
| + | //Figure 7.16. PIC32 PMP interface with LCD.// | ||
| + | |||
| + | Since the some of the pins used for the LCD interface with the PIC32MX370 processor are either analog inputs or digital I/O, it is necessary to first declare all LCD interface pins as digital by either using the PLIB function // | ||
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| - | ==== Listing | + | ==== Listing |
| < | < | ||
| int cfg1 = PMP_ON|PMP_READ_WRITE_EN|PMP_READ_POL_HI|PMP_WRITE_POL_HI; | int cfg1 = PMP_ON|PMP_READ_WRITE_EN|PMP_READ_POL_HI|PMP_WRITE_POL_HI; | ||
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| ---- | ---- | ||
| - | The first bit parameter in the variable //cfg1// enables the PMP peripheral. The second bit parameter enables both of the PMP read and write operations. The PMP_READ_POL_HI bit with the PMP_WRITE_POL_HI bit results in setting the last two significant bits of the PMCON register, and it indicates that the PMP read/write control is to be high when reading and low when writing. The interpretation of these two bits is conditional on the PMP_MODE_MASTER1 control bits of the PMMODE register and implementation is done via the handshaking operation illustrated back in Fig. 6.4. The variable //cfg2// is written to the PMMODE register. The PMP_DATA_BUS_ 8-bit control specifies that the data bus is 8 bits. The three PMP_WAIT controls are discussed in detail below. | + | The first bit parameter in the variable //cfg1// enables the PMP peripheral. The second bit parameter enables both of the PMP read and write operations. The PMP_READ_POL_HI bit with the PMP_WRITE_POL_HI bit results in setting the last two significant bits of the PMCON register, and it indicates that the PMP read/write control is to be high when reading and low when writing. The interpretation of these two bits is conditional on the PMP_MODE_MASTER1 control bits of the PMMODE register and implementation is done via the handshaking operation illustrated back in Fig. 7.4. The variable //cfg2// is written to the PMMODE register. The PMP_DATA_BUS_ 8-bit control specifies that the data bus is 8 bits. The three PMP_WAIT controls are discussed in detail below. |
| The //cfg3// variable is set for PMP_PEN_0, indicating that only PMP address bit 0 is enabled and is written to the parallel port address register, PMADDR. | The //cfg3// variable is set for PMP_PEN_0, indicating that only PMP address bit 0 is enabled and is written to the parallel port address register, PMADDR. | ||
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| The last parameter disables PMP interrupts. If the PMP interrupt is enabled, with the PMP configured for the master mode, an interrupt will be generated on every completed read and write operation. With the PMP interrupt disabled, the PMFLAG will need to be polled to determine when the PMP read and write cycles are completed. | The last parameter disables PMP interrupts. If the PMP interrupt is enabled, with the PMP configured for the master mode, an interrupt will be generated on every completed read and write operation. With the PMP interrupt disabled, the PMFLAG will need to be polled to determine when the PMP read and write cycles are completed. | ||
| - | The WAIT controls in the PMP mode register control the timing of the assertion of the RD/WR select signal in relation to the LCD Enable strobe. Each vertical dashed line in Fig. 6.20 represents intervals of the peripheral bus clock period, marked T< | + | The WAIT controls in the PMP mode register control the timing of the assertion of the RD/WR select signal in relation to the LCD Enable strobe. Each vertical dashed line in Fig. 7.17 represents intervals of the peripheral bus clock period, marked T< |
| - | {{ : | ||
| - | //Figure 6.18. The PMP timing diagram for the beginning, middle, and end wait periods.// | ||
| - | The minimum settings for the three PMP WAIT intervals can be determined by dividing the value for t< | + | {{ : |
| + | //Figure 7.17. The PMP timing diagram for the beginning, middle, and end wait periods.// | ||
| + | |||
| + | The minimum settings for the three PMP WAIT intervals can be determined by dividing the value for t< | ||
| + | |||
| + | < | ||
| + | (1) $[B+(M+1)+E] * T_PB$ | ||
| + | |||
| + | (2) $[B+(M+1)+E] * T_PB = (5) * 100 ns = 500 ns$ | ||
| + | < | ||
| + | |||
| + | Since the PMP is clocked from the peripheral bus clock, it is likely that the PMP cycle is slower than the core CPU, which means that the PMP also has a busy flag that must be polled before writing or reading the next byte. With the PMP interrupt disabled, the only way to determine if the PMP is ready for the next read or write cycle is to poll the PMP flag. The // | ||
| - | Since the PMP is clocked from the peripheral bus clock, it is likely that the PMP cycle is slower than the core CPU, which means that the PMP also has a busy flag that must be polled before writing or reading the next byte. With the PMP interrupt disabled, the only way to determine if the PMP is ready for the next read or write cycle is to poll the PMP flag. The // | ||
| ---- | ---- | ||
| - | ==== Listing | + | ==== Listing |
| < | < | ||
| void writeLCD( int addr, char c) | void writeLCD( int addr, char c) | ||
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| ---- | ---- | ||
| - | Reading the PMP requires two successive read operations, as shown in Listing | + | Reading the PMP requires two successive read operations, as shown in Listing |
| ---- | ---- | ||
| - | ==== Listing | + | ==== Listing |
| < | < | ||
| char readLCD( int addr ) | char readLCD( int addr ) | ||
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| ===== Appendix A: Unit 3 Parts Configuration ===== | ===== Appendix A: Unit 3 Parts Configuration ===== | ||
| - | {{ : | + | {{ : |
| //Figure A.1. LCD connection schematic diagram for Labs 3a and 3b.// | //Figure A.1. LCD connection schematic diagram for Labs 3a and 3b.// | ||
| - | |||
| ---- | ---- | ||
| ===== Appendix B: LCD Custom Instrumentation ===== | ===== Appendix B: LCD Custom Instrumentation ===== | ||
| - | A prototype of the Basys MX3 was specially instrumented so that an Analog Discovery 2 can be connected | + | As noted above in section 4.2, Fig. B.2 through Fig. B.4 show data from an Analog Discovery 2 connected |
| - | {{ : | + | Note the Analog Discovery 2 is not connected directly to the on-board 30-pin Analog Discovery 2 connector, J4, in this case because the LCD data pins are not broken out to the Analog Discovery Interface connector. |
| + | |||
| + | {{ : | ||
| //Figure B.1. Equipment configuration used in Lab 3a and 3b for Unit 3.// | //Figure B.1. Equipment configuration used in Lab 3a and 3b for Unit 3.// | ||
| - | The alternate method is to read the LCD Busy Flag before any instruction is written or read. As stated above, there is no waiting to read the Busy Flag. Figure B.2 is a screen capture of this operation. The Busy Flag and DDRAM address is initially read as 0x4c, meaning that the cursor is located at the 12th character position on the second line and the Busy Flag is off. Following that, a new cursor position, 0x48, is written to the LCD. The value shown in Fig. B.2 is 0xC8 because the 8th bit is set to instruct the LCD to move the cursor to a new position using the “Set DDRAM Address” instruction. The Busy Flag and DDRAM address is read six consecutive times. The busy flag is set high the first five times. The sixth time the busy flag is set low (not busy) and the address shows 0x48, meaning the cursor position is now located for the eighth character position of the second row. The period the Busy Flag reads high for is 33.6 μs. This is consistent with the 39 μs listed in Fig. 6.14. Again, the execution times shown in Fig. 6.14 are worst case and dependent on operating temperature and supply voltage. | + | The alternate method |
| - | {{ : | + | {{ : |
| - | //Figure B.2. LCD timing diagram for a Set Cursor Position instruction using 1 s setup and EN extension delays.// | + | //Figure B.2. LCD timing diagram for a Set Cursor Position instruction using 1 μs setup and EN extension delays.// |
| Figure B.3 shows the timing for the Set Cursor Position instruction where the read cycle speed is increased by a factor of 10. Note that the period waiting for the instruction execution to complete is still 33.6 μs, thus showing the LCD processing time is independent of the processor to LCD interface speed. | Figure B.3 shows the timing for the Set Cursor Position instruction where the read cycle speed is increased by a factor of 10. Note that the period waiting for the instruction execution to complete is still 33.6 μs, thus showing the LCD processing time is independent of the processor to LCD interface speed. | ||
| - | {{ : | + | {{ : |
| - | //Figure B.3. LCD timing diagram for a Set Cursor Position instruction using 0.1 s setup and EN extension delays.// | + | //Figure B.3. LCD timing diagram for a Set Cursor Position instruction using 0.1 μs setup and EN extension delays.// |
| - | Figure B.4 shows the similar timing of the Set Cursor Position when the PMP interface to the LCD is used in place of the Bit-Banging type of parallel bus control. As one can readily see, the LCD response in Fig. B.3 is very similar to Fig. B.4; however, as discussed in Section | + | Figure B.4 shows the similar timing of the Set Cursor Position when the PMP interface to the LCD is used in place of the Bit-Banging type of parallel bus control. As one can readily see, the LCD response in Fig. B.3 is very similar to Fig. B.4; however, as discussed in Section |
| - | {{ : | + | {{ : |
| //Figure B.4. LCD timing diagram for a Set Cursor Position instruction using the PIC32 PMP interface.// | //Figure B.4. LCD timing diagram for a Set Cursor Position instruction using the PIC32 PMP interface.// | ||
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| There is a 64-byte block of RAM (random-access memory) that the LCD controller uses in the same way as it does the ROM-based character-generator. This is the CGRAM. When the controller receives an ASCII code in the range that's mapped to the CGRAM, it uses the bit patterns stored there to display a pattern on the LCD. The main difference is that you can write to CGRAM, thereby defining your own graphic symbols. | There is a 64-byte block of RAM (random-access memory) that the LCD controller uses in the same way as it does the ROM-based character-generator. This is the CGRAM. When the controller receives an ASCII code in the range that's mapped to the CGRAM, it uses the bit patterns stored there to display a pattern on the LCD. The main difference is that you can write to CGRAM, thereby defining your own graphic symbols. | ||
| - | A character LCD that uses the HD44780 or the KS0068 controller allows for eight programmable characters. The character patterns must initially be programmed into the CGRAM of the LCD. First, the CGRAM must be selected by setting the CGRAM address for the character that is to be programmed. Each eight consecutive addresses, starting at CGRAM address zero, are assigned to one programmable graphical character. Each bit of the data at each address sets the pixel on (1) or off (0). The pixels on a particular row at the right of the character display have the lowest binary value. The rows of pixels start at the top and move down the character as the addresses increase in value, as shown in Fig. B.1. | + | A character LCD that uses the HD44780 or the KS0068 controller allows for eight programmable characters. The character patterns must initially be programmed into the CGRAM of the LCD. First, the CGRAM must be selected by setting the CGRAM address for the character that is to be programmed. Each eight consecutive addresses, starting at CGRAM address zero, are assigned to one programmable graphical character. Each bit of the data at each address sets the pixel on (1) or off (0). The pixels on a particular row at the right of the character display have the lowest binary value. The rows of pixels start at the top and move down the character as the addresses increase in value, as shown in Fig. C.1. |
| {{ : | {{ : | ||
| //Figure C.1. Example bitmap for a programmable graphical character.// | //Figure C.1. Example bitmap for a programmable graphical character.// | ||
| + | A web-based character calculator can be used to help determine the list of bytes that need to be written to the CGRAM. Be advised that the calculator in the second reference only generates seven bytes of data and does not specify data for the bottom row of pixels. Writing to CGRAM is a lot like moving the cursor to a particular position on the display and displaying characters at that new location. The steps are shown in Listing C.1. | ||
| ---- | ---- | ||
| ==== Listing C.1. Steps to Program Graphical Characters ===== | ==== Listing C.1. Steps to Program Graphical Characters ===== | ||
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