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learn:courses:unit-2:start [2017/06/09 21:29] – [Listing 7.6. Timer 1 ISR at Interrupt Level 2] brandon marcumlearn:courses:unit-2:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 [[{}/learn/courses/microprocessor-io-unit-1/start|Back to Unit 1]] [[{}/learn/courses/microprocessor-io-unit-1/start|Back to Unit 1]]
 ==Unit 2 Labs== ==Unit 2 Labs==
-  * [[https://reference.digilentinc.com/learn/courses/unit-2-lab2a/start|Lab 2a]] +  * [[/learn/courses/unit-2-lab2a/start|Lab 2a]] 
-  * [[https://reference.digilentinc.com/learn/courses/unit-2-lab2b/start|Lab 2b]]+  * [[/learn/courses/unit-2-lab2b/start|Lab 2b]]
  
  
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 ===== 4. Unit Equipment List ===== ===== 4. Unit Equipment List =====
 ==== 4.1. Hardware ==== ==== 4.1. Hardware ====
-  - [[http://store.digilentinc.com/basys-mx3-pic32mx-trainer-board-recommended-for-embedded-systems-courses/|Basys MX3 trainer board]] +  - [[https://digilent.com/shop/basys-mx3-pic32mx-trainer-board-for-embedded-systems-courses/|Basys MX3 trainer board]] 
-  - [[http://store.digilentinc.com/usb-a-to-micro-b-cable/|Micro USB cable]]+  - [[https://digilent.com/shop/usb-a-to-micro-b-cable/|Micro USB cable]]
   - Workstation computer running Windows 10 or higher, MAC OS, or Linux   - Workstation computer running Windows 10 or higher, MAC OS, or Linux
-  - [[http://store.digilentinc.com/stepper-motor/|4-wire stepper motor]] +  - [[https://digilent.com/shop/stepper-motor/|4-wire stepper motor]] 
-  - [[http://store.digilentinc.com/5v-4000ma-switching-power-supply/|5V, 4A DC power supply]]+  - [[https://digilent.com/shop/5v-4a-switching-power-supply/|5V, 4A DC power supply]]
  
 ==== 4.2. Software ==== ==== 4.2. Software ====
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 The correct operation of a dynamic real-time scheduling scheme is predicated on two requirements. The first is that the worst case (longest) execution time of the timer interrupt service routine (ISR) must be less than the interrupt interval. The second is that the time remaining in the interrupt period after execution of the ISR must be sufficient so that it appears to the user that the processor is acknowledging his or her inputs in a timely manner. The correct operation of a dynamic real-time scheduling scheme is predicated on two requirements. The first is that the worst case (longest) execution time of the timer interrupt service routine (ISR) must be less than the interrupt interval. The second is that the time remaining in the interrupt period after execution of the ISR must be sufficient so that it appears to the user that the processor is acknowledging his or her inputs in a timely manner.
  
-Real-time operation has two basic requirements: correct value at the correct time. A system that cannot always meet both of these requirements is a failed system. Hence, it is not sufficient to just have the correct output values; these outputs have to be generated at the correct time. You have already developed a real-time operating system for [[https://reference.digilentinc.com/learn/courses/microprocessor-io-lab-1b/start|Lab 1b]].+Real-time operation has two basic requirements: correct value at the correct time. A system that cannot always meet both of these requirements is a failed system. Hence, it is not sufficient to just have the correct output values; these outputs have to be generated at the correct time. You have already developed a real-time operating system for [[/learn/courses/microprocessor-io-lab-1b/start|Lab 1b]].
  
 The time required to service the ISR includes the execution time of the user ISR code in addition to the time required to save and restore the system context. Using the MPLAB X Stopwatch debugging feature, we find that it requires 33 machine cycles to save and restore the system context. Using a core frequency of 80 MHz, the context saving and restoring time is 1.03 μs. The time to execute the user written code varies. In the case of Labs 2a and 2b, execution of the ISR code will vary based upon the conditional execution of the LED and stepper motor functions. The time required to service the ISR includes the execution time of the user ISR code in addition to the time required to save and restore the system context. Using the MPLAB X Stopwatch debugging feature, we find that it requires 33 machine cycles to save and restore the system context. Using a core frequency of 80 MHz, the context saving and restoring time is 1.03 μs. The time to execute the user written code varies. In the case of Labs 2a and 2b, execution of the ISR code will vary based upon the conditional execution of the LED and stepper motor functions.