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learn:courses:unit-2:start [2017/06/08 22:42] – [Listing A.3. Example Timer Delay Using Interrupt Flag Polling] brandon marcumlearn:courses:unit-2:start [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 [[{}/learn/courses/microprocessor-io-unit-1/start|Back to Unit 1]] [[{}/learn/courses/microprocessor-io-unit-1/start|Back to Unit 1]]
 ==Unit 2 Labs== ==Unit 2 Labs==
-  * [[https://reference.digilentinc.com/learn/courses/unit-2-lab2a/start|Lab 2a]] +  * [[/learn/courses/unit-2-lab2a/start|Lab 2a]] 
-  * [[https://reference.digilentinc.com/learn/courses/unit-2-lab2b/start|Lab 2b]]+  * [[/learn/courses/unit-2-lab2b/start|Lab 2b]]
  
  
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 ===== 4. Unit Equipment List ===== ===== 4. Unit Equipment List =====
 ==== 4.1. Hardware ==== ==== 4.1. Hardware ====
-  - [[http://store.digilentinc.com/basys-mx3-pic32mx-trainer-board-recommended-for-embedded-systems-courses/|Basys MX3 trainer board]] +  - [[https://digilent.com/shop/basys-mx3-pic32mx-trainer-board-for-embedded-systems-courses/|Basys MX3 trainer board]] 
-  - [[http://store.digilentinc.com/usb-a-to-micro-b-cable/|Micro USB cable]]+  - [[https://digilent.com/shop/usb-a-to-micro-b-cable/|Micro USB cable]]
   - Workstation computer running Windows 10 or higher, MAC OS, or Linux   - Workstation computer running Windows 10 or higher, MAC OS, or Linux
-  - [[http://store.digilentinc.com/stepper-motor/|4-wire stepper motor]] +  - [[https://digilent.com/shop/stepper-motor/|4-wire stepper motor]] 
-  - [[http://store.digilentinc.com/5v-4000ma-switching-power-supply/|5V, 4A DC power supply]]+  - [[https://digilent.com/shop/5v-4a-switching-power-supply/|5V, 4A DC power supply]]
  
 ==== 4.2. Software ==== ==== 4.2. Software ====
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 The correct operation of a dynamic real-time scheduling scheme is predicated on two requirements. The first is that the worst case (longest) execution time of the timer interrupt service routine (ISR) must be less than the interrupt interval. The second is that the time remaining in the interrupt period after execution of the ISR must be sufficient so that it appears to the user that the processor is acknowledging his or her inputs in a timely manner. The correct operation of a dynamic real-time scheduling scheme is predicated on two requirements. The first is that the worst case (longest) execution time of the timer interrupt service routine (ISR) must be less than the interrupt interval. The second is that the time remaining in the interrupt period after execution of the ISR must be sufficient so that it appears to the user that the processor is acknowledging his or her inputs in a timely manner.
  
-Real-time operation has two basic requirements: correct value at the correct time. A system that cannot always meet both of these requirements is a failed system. Hence, it is not sufficient to just have the correct output values; these outputs have to be generated at the correct time. You have already developed a real-time operating system for [[https://reference.digilentinc.com/learn/courses/microprocessor-io-lab-1b/start|Lab 1b]].+Real-time operation has two basic requirements: correct value at the correct time. A system that cannot always meet both of these requirements is a failed system. Hence, it is not sufficient to just have the correct output values; these outputs have to be generated at the correct time. You have already developed a real-time operating system for [[/learn/courses/microprocessor-io-lab-1b/start|Lab 1b]].
  
 The time required to service the ISR includes the execution time of the user ISR code in addition to the time required to save and restore the system context. Using the MPLAB X Stopwatch debugging feature, we find that it requires 33 machine cycles to save and restore the system context. Using a core frequency of 80 MHz, the context saving and restoring time is 1.03 μs. The time to execute the user written code varies. In the case of Labs 2a and 2b, execution of the ISR code will vary based upon the conditional execution of the LED and stepper motor functions. The time required to service the ISR includes the execution time of the user ISR code in addition to the time required to save and restore the system context. Using the MPLAB X Stopwatch debugging feature, we find that it requires 33 machine cycles to save and restore the system context. Using a core frequency of 80 MHz, the context saving and restoring time is 1.03 μs. The time to execute the user written code varies. In the case of Labs 2a and 2b, execution of the ISR code will vary based upon the conditional execution of the LED and stepper motor functions.
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 ==== Listing 7.6. Timer 1 ISR at Interrupt Level 2 ==== ==== Listing 7.6. Timer 1 ISR at Interrupt Level 2 ====
 <code> <code>
-void __ISR(_TIMER_1_VECTOR, IPL2) Timer1Handler(void) +void __ISR(_TIMER_1_VECTOR, IPL2SOFT) Timer1Handler(void) 
 {  {
  
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 The maximum counter value is determined by the size of the register that holds the counts. Common sizes for microprocessors are 8-, 16-, and 32-bit. Including the core timer, the PIC32 processor has six timers that can be used for delay timing. The core timer is 32 bits wide. Timers 2 and 3 along with Timers 4 and 5 can be used together as 32-bit counters, respectively, extending the count value range from 65,536 to 4,294,967,296. As shown in Fig. A.3, when the counter register equals the value of the period register (PR), the counter is reset to zero and the timer interrupt flag is set. Although the core timer can be reset to any value, PIC32 documentation recommends that such practices be avoided.  The maximum counter value is determined by the size of the register that holds the counts. Common sizes for microprocessors are 8-, 16-, and 32-bit. Including the core timer, the PIC32 processor has six timers that can be used for delay timing. The core timer is 32 bits wide. Timers 2 and 3 along with Timers 4 and 5 can be used together as 32-bit counters, respectively, extending the count value range from 65,536 to 4,294,967,296. As shown in Fig. A.3, when the counter register equals the value of the period register (PR), the counter is reset to zero and the timer interrupt flag is set. Although the core timer can be reset to any value, PIC32 documentation recommends that such practices be avoided. 
  
-The period register is used to set the timer’s maximum count. If a period equal to a value of N is set, then N-1 is written to the PR register. The period registers are declared as PR1 for Timer 1, PR2 for Timer 2, and so on. Each Timer 1 count is compared to the value of the PR1 register. When the PR1 register equals the Timer 1 register, the timer has reached its terminal count and initiates two actions: first, the Timer 1 register is reset to zero, and second, the Timer 1 Interrupt Flag (T1IF) bit is set in the Interrupt Flag Status register (IFS0). (See the [[http://ww1.microchip.com/downloads/en/DeviceDoc/61156G.pdf|PIC32MX3xx/4xx/5xx User’s Manual]] Sheet Section 7, Table 7-1 for additional information.) +The period register is used to set the timer’s maximum count. If a period equal to a value of N is set, then N-1 is written to the PR register. The period registers are declared as PR1 for Timer 1, PR2 for Timer 2, and so on. Each Timer 1 count is compared to the value of the PR1 register. When the PR1 register equals the Timer 1 register, the timer has reached its terminal count and initiates two actions: first, the Timer 1 register is reset to zero, and second, the Timer 1 Interrupt Flag (T1IF) bit is set in the Interrupt Flag Status register (IFS0). (See the [[http://ww1.microchip.com/downloads/en/DeviceDoc/60001185F.pdf|PIC32MX3xx/4xx/5xx User’s Manual]] Sheet Section 7, Table 7-1 for additional information.) 
  
 As Fig. A.3 illustrates, the Timer 1 clock frequency (T1CLK) is determined from the crystal frequency on the Basys MX3 trainer board (XTAL), the PLL input divider (FPLLIDIV), the PLL multiplier (FPLLMUL), the PLL output divider (FPLLODIV), the peripheral bus clock divider (FPBDIV), and the Timer pre-scale (TCKPS). This frequency is computed using Eq.1. The values of XTAL, FPLLMUL, FPLLDIV, FPLLODIV, and FPBDIV are set in the common “config_bits.h” header file.   As Fig. A.3 illustrates, the Timer 1 clock frequency (T1CLK) is determined from the crystal frequency on the Basys MX3 trainer board (XTAL), the PLL input divider (FPLLIDIV), the PLL multiplier (FPLLMUL), the PLL output divider (FPLLODIV), the peripheral bus clock divider (FPBDIV), and the Timer pre-scale (TCKPS). This frequency is computed using Eq.1. The values of XTAL, FPLLMUL, FPLLDIV, FPLLODIV, and FPBDIV are set in the common “config_bits.h” header file.  
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 * *
 * Oscillator Configuration Bit Settings: config_bits.h * Oscillator Configuration Bit Settings: config_bits.h
-* Basys MX3 hardware initialization is provided by Hardware_Setup.c +* Basys MX3 hardware initialization is provided by hardware.c and should be included as a project source file.
 * Notes: * Notes:
 *   - Peripheral clock: BPCLK = FOSC/PB_DIV = 80E6/8 = 10MHz *   - Peripheral clock: BPCLK = FOSC/PB_DIV = 80E6/8 = 10MHz
 *   - Timer 1 clock = T1_CLK = PBCLK / T1PS = 10E6 / 8 = 1.25E5 *   - Timer 1 clock = T1_CLK = PBCLK / T1PS = 10E6 / 8 = 1.25E5
-*   - To generate a 1 ms delay, PR1 is loaded with T1_TICK = (1250-1) = 1249+*   - To generate a 1 ms delay, PR1 is loaded with T1_TICK - 1 = (1250 - 1) = 1249
 * *
 ********************************************************************/ ********************************************************************/
-#include "config_bits.h" 
 #include <plib.h> #include <plib.h>
 +#include "config_bits.h"
 +#include "hardware.h"
  
 /* Application constant */ /* Application constant */
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 /********************************************************************* /*********************************************************************
 * The purpose of this example code is to demonstrate the use of the Type A  * The purpose of this example code is to demonstrate the use of the Type A 
-* Timer 1 interrupts to generate a 1 ms delay.+* Timer 1 interrupts to generate a 1 second delay.
 * *
 * Platform:     Basys MX3  * Platform:     Basys MX3 
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 * *
 * Oscillator Configuration Bit Settings: config_bits.h * Oscillator Configuration Bit Settings: config_bits.h
-* Basys MX3 hardware initialization is provided by Hardware_Setup.c +* Basys MX3 hardware initialization is provided by hardware.c 
 * Notes: * Notes:
 *        - Peripheral Clock: PBCLK = 80E6 / 8 = 10E6  *        - Peripheral Clock: PBCLK = 80E6 / 8 = 10E6 
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 * *
 ********************************************************************/ ********************************************************************/
 +
 +#include <plib.h>       /* Include peripheral library */
 #include "config_bits.h"   /* System configuration */ #include "config_bits.h"   /* System configuration */
-#include <plib.h>    /* Include peripheral library */+#include "hardware.h"      /* Includes GetPeripheralClock() */
                                                
 /* Application constant */ /* Application constant */
-#define T1_PRESCALE      8 +#define T1_PRESCALE      256 
-#define TOGGLES_PER_SEC  1000+#define TOGGLES_PER_SEC  1
 #define T1_TICK          (GetPeripheralClock() / T1_PRESCALE / TOGGLES_PER_SEC) #define T1_TICK          (GetPeripheralClock() / T1_PRESCALE / TOGGLES_PER_SEC)
  
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        /* Code background tasks */        /* Code background tasks */
    }     } 
-   return (EXIT_FAILURE);  /* System has failed is this line is reached */+   return (EXIT_FAILURE);  /* System has failed if this line is reached */
 } /* End of main */  } /* End of main */ 
  
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 * SYNTAX:         void __ISR(_TIMER_1_VECTOR, IPL2SOFT) Timer1Handler(void) * SYNTAX:         void __ISR(_TIMER_1_VECTOR, IPL2SOFT) Timer1Handler(void)
 * KEYWORDS:       millisecond, hardware delay, Timer A, timer * KEYWORDS:       millisecond, hardware delay, Timer A, timer
-* DESCRIPTION:    Services the Timer 1 interrupt and toggles LED1+* DESCRIPTION:    Services the Timer 1 interrupt and toggles LED0
 * Parameters:     None * Parameters:     None
 * RETURN:         None * RETURN:         None