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| learn:courses:unit-2-lab2b:start [2018/01/11 19:32] – James Colvin | learn:courses:unit-2-lab2b:start [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ===== 3. Equipment List ===== | ===== 3. Equipment List ===== | ||
| ==== 3.1. Hardware ==== | ==== 3.1. Hardware ==== | ||
| - | - [[http://store.digilentinc.com/ | + | - [[https://digilent.com/shop/ |
| - | - [[http://store.digilentinc.com/ | + | - [[https://digilent.com/shop/ |
| - Workstation computer running Windows 10 or higher, MAC OS, or Linux | - Workstation computer running Windows 10 or higher, MAC OS, or Linux | ||
| - | - [[http://store.digilentinc.com/ | + | - [[https://digilent.com/shop/ |
| - | - [[http://store.digilentinc.com/ | + | - [[https://digilent.com/shop/ |
| In addition, we suggest the following instruments: | In addition, we suggest the following instruments: | ||
| Line 40: | Line 40: | ||
| - [[http:// | - [[http:// | ||
| - [[http:// | - [[http:// | ||
| - | - [[http://store.digilentinc.com/ | + | - [[https://digilent.com/shop/ |
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| - Concept maps | - Concept maps | ||
| - Develop a Data flow diagram that relates slide switch inputs, push button inputs, and timer interrupts to stepper motor and seven segment LED outputs. | - Develop a Data flow diagram that relates slide switch inputs, push button inputs, and timer interrupts to stepper motor and seven segment LED outputs. | ||
| - | - Develop a state transition diagram similar to the one described in [[https:// | + | - Develop a state transition diagram similar to the one described in [[/ |
| - Develop a control flow diagram that describes the total system operation. Background operations are represented separately from each foreground operation. | - Develop a control flow diagram that describes the total system operation. Background operations are represented separately from each foreground operation. | ||
| - Review the pertinent schematic diagrams to determine the relevant IO pin assignments. Refer to Figs. A.3, A.4, and A.5 in Appendix A. | - Review the pertinent schematic diagrams to determine the relevant IO pin assignments. Refer to Figs. A.3, A.4, and A.5 in Appendix A. | ||

