Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
genesys:refmanual [2014/09/12 19:05] – [PS/2 Port] Joshua Woldstadgenesys:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 531: Line 531:
 ====== Expansion Connectors ====== ====== Expansion Connectors ======
  
-The Genesys board offers two 68-pin VHDC connectors for high-speed parallel I/O, and four 8-pin Pmod connectors for lower speed and lower pin-count I/O. Data sheets for VHDC connectors can be found on the Digilent website and on many vendor and distributor websites as well. +The Genesys board offers two 68-pin VHDC connectors for high-speed parallel I/O, and four 8-pin Pmod ports for lower speed and lower pin-count I/O. Data sheets for VHDC connectors can be found on the Digilent website and on many vendor and distributor websites as well. 
  
 The VHDC connectors include 40 data signals (routed as 20 impedance-controlled matched pairs), 20 grounds (one per pair), and eight power signals. These connectors, commonly used for SCSI-3 applications, can accommodate data rates of several hundred megahertz on every pin. Both board-to-board and board-to-cable mating connectors are available. Digilent and several distributors carry mating connectors and cables of various lengths. The VHDC connectors include 40 data signals (routed as 20 impedance-controlled matched pairs), 20 grounds (one per pair), and eight power signals. These connectors, commonly used for SCSI-3 applications, can accommodate data rates of several hundred megahertz on every pin. Both board-to-board and board-to-cable mating connectors are available. Digilent and several distributors carry mating connectors and cables of various lengths.
Line 541: Line 541:
  
 {{ :genesys:exp1.png?600 |}} {{ :genesys:exp1.png?600 |}}
 +
 +The Genesys board’s unregulated input voltage (VU) is routed to the four center pins of the connector, providing up to 1A of current (250mA per pin) to connected boards. VU is routed to the connectors through the main power switch, and through jumper JP1 (so that VU can be removed from peripheral boards if desired).
 +
 +All I/O pins on connector J1 are routed to FPGA I/O bank 11, and all I/O pins on connector J2 are routed to FPGA I/O bank 13. The VCC voltage driving these I/O banks is also routed to four VCC pins on each connector, using pins immediately distal to the four VU pins. The shared I/O bank and connector VCC may be set to 3.3V, 2.5V, left unconnected or driven from an external source using jumpers JP11 (J1) and JP12 (J2). 
 +
 +
 +{{ :genesys:exp2.png?450 |}}
 +
 +|  **VHDC Connector J1**                       |||| **VHDC Connector J2**                         ||||
 +| Name                    | Pin  | Name    | Pin  | Name                   | Pin   | Name    | Pin   |
 +| IO1-P                   | B32  | IO1-N   | A33  | IO21-P                 | W34   | IO21-N  | V34   |
 +| IO2-P                   | C32  | IO2-N   | D32  | IO22-P                 | V32   | IO22-N  | V33   |
 +| IO3-P                   | B33  | IO3-N   | C33  | IO23-P                 | AA34  | IO23-N  | Y34   |
 +| IO4-P                   | E32  | IO4-N   | E33  | IO24-P                 | Y33   | IO24-N  | AA33  |
 +| IO5-P                   | C34  | IO5-N   | D34  | IO25-P                 | AC33  | IO25-N  | AB33  |
 +| IO6-P                   | G32  | IO6-N   | H32  | IO26-P                 | Y32   | IO26-N  | W32   |
 +| IO7-P                   | F33  | IO7-N   | E34  | IO27-P                 | AC34  | IO27-N  | AD34  |
 +| IO8-P                   | J32  | IO8-N   | H33  | IO28-P                 | AC32  | IO28-N  | AB32  |
 +| IO9-P                   | G33  | IO9-N   | F34  | IO29-P                 | AF34  | IO29-N  | AE34  |
 +| IO10-P                  | K33  | IO10-N  | K32  | IO30-P                 | AF33  | IO30-N  | AE33  |
 +| IO11-P                  | H34  | IO11-N  | J34  | IO31-P                 | AG33  | IO31-N  | AH33  |
 +| IO12-P                  | L34  | IO12-N  | K34  | IO32-P                 | AH34  | IO32-N  | AJ34  |
 +| IO13-P                  | L33  | IO13-N  | M32  | IO33-P                 | AD32  | IO33-N  | AE32  |
 +| IO14-P                  | N33  | IO14-N  | M33  | IO34-P                 | AK34  | IO34-N  | AK33  |
 +| IO15-P                  | P32  | IO15-N  | N32  | IO35-P                 | AG32  | IO35-N  | AH32  |
 +| IO16-P                  | P34  | IO16-N  | N34  | IO36-P                 | AM33  | IO36-N  | AM32  |
 +| IO17-P                  | R33  | IO17-N  | R32  | IO37-P                 | AJ32  | IO37-N  | AK32  |
 +| IO18-P                  | T33  | IO18-N  | R34  | IO38-P                 | AN34  | IO38-N  | AN33  |
 +| IO19-P                  | U32  | IO19-N  | U31  | IO39-P                 | AL34  | IO39-N  | AL33  |
 +| IO20-P                  | U33  | IO20-N  | T34  | IO40-P                 | AN32  | IO40-N  | AP32  |
 +
 +
 +Pmods use 2x6 right-angle, 100-mil connectors that mate with standard 2x6 pin headers available from a variety of catalog distributors. Each 12-pin Pmod port provides two VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals. VCC and Ground pins can deliver up to 1A of current, and a jumper block is available for each connector to choose the VCC voltage: regulated 3.3V or the unregulated board input voltage (VU). Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching.
 +
 +{{ :genesys:exp3.png?600 |}}
 +
 +Digilent produces a large collection of accessory boards that can attach to the Pmod and VHDC expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, cameras and other functions. See www.digilentinc.com for more information.
 +
 +|  **Pmod Port Pinouts**                                                                        ||||||||
 +|  **Pmod A**                         ||  **Pmod B**         ||  **Pmod C**         ||  **Pmod D**         ||
 +| Signal                       | Pin   | Signal       | Pin   | Signal       | Pin   | Signal       | Pin   |
 +| JA1                          | AD11  | JB1          | AE9   | JC1          | AL11  | JD1          | AN14  |
 +| JA2                          | AD9   | JB2          | AC8   | JC2          | AJ10  | JD2          | AN13  |
 +| JA3                          | AM13  | JB3          | AB10  | JC3          | AK9   | JD3          | AP12  |
 +| JA4                          | AM12  | JB4          | AC9   | JC4          | AF9   | JD4          | AL10  |
 +| JA7                          | AD10  | JB7          | AF8   | JC7          | AK11  | JD7          | AP14  |
 +| JA8                          | AE8   | JB8          | AB8   | JC8          | AC10  | JD8          | AN12  |
 +| JA9                          | AF10  | JB9          | AA10  | JC9          | AJ9   | JD9          | AM11  |
 +| JA10                         | AJ11  | JB10         | AA9   | JC10         | AA8   | JD10         | AK8   |
 +
 +
 +----
 +
 +====== System Monitor ======
 +
 +The Genesys board supports the dedicated analog inputs (VP and VN pins on J13) to the Virtex 5 FPGA System Monitor block. The PCB layout for the VP and VN pins is designed using differential pairs and anti-alias filtering in close proximity to the FPGA as recommended in the Virtex 5 FPGA System Monitor User Guide. The Virtex 5 FPGA System Monitor function is built around a 10-bit, 200-kSPS Analog-to-Digital Converter (ADC). The System Monitor is fully functional on power up, and measurement data can be accessed via the JTAG port pre-configuration. The Xilinx ChipScope™ Pro tool provides access to the System Monitor over the JTAG port. The System Monitor control logic implements some common monitoring features. For example, an automatic channel sequencer allows a user-defined selection of parameters to be automatically monitored, and user-programmable averaging is enabled to ensure robust noise-free measurements.
 +
 +The System Monitor also provides user-programmable alarm thresholds for the on-chip sensors. Thus, if an on-chip monitored parameter moves outside the user-specified operating range, an alarm logic output becomes active. In addition to monitoring the on-chip temperature for user-defined applications, the System Monitor issues a special alarm called Over-Temperature (OT) if the FPGA temperature becomes critical (> 125°C). The OT signal is deactivated when the device temperature falls below a user specified lower limit. If the FPGA power-down feature is enabled, the FPGA enters power down when the OT signal becomes active. The FPGA powers up again when the alarm is deactivated. For additional information about the System Monitor, see http://www.xilinx.com/systemmonitor and consult the Virtex 5 FPGA System Monitor User Guide. The table below shows the System Monitor connections.
 +
 +
 +|  **J13 Pin**  |  **Signal**  |  **Function**                                                       |
 +| 1             | DXP          | Anode of the FPGA temperature-sensing diode                         |
 +| 2             | VP           | System Monitor dedicated differential analog input (positive side)  |
 +| 3             | DXN          | Cathode of the FPGA temperature-sensing diode                       |
 +| 4             | VN           | System Monitor dedicated differential analog input (negative side)  |
 +| 5             | GND          |                                                                     |
 +| 6             | GND          |                                                                     |
 +
 +
 +----
 +
 +====== Built-In Self Test ======
 +
 +A demonstration configuration is loaded into the StataFlash ROM on the Genesys board during manufacturing. This demo, also available on the Digilent website, can serve as a board verification test since it interacts with all devices and ports on the board. To configure the FPGA from the demo file stored in StrataFlash, set the mode jumper to BPI UP and cycle power. When Genesys powers up, the DDR is tested, and then an image file will be transferred from the StrataFlash into DDR2. This image will be driven out the HDMI port for display on a DVI/HDMI compatible monitor. The slide switches are connected to the user LEDs, and user buttons BTN0, BTN1, and BTN3 cause varying sine-wave frequencies to be driven on the LINE IN and LINE OUT audio ports.  The LCD screen (DISP1) will initially display “Genesys User Demo / BIST” on startup, and then display text whenever the state of a user button or switch is changed.
 +
 +If the self test is not resident in the StrataFlash ROM, it can be programmed into the FPGA or reloaded into the ROM using the Adept programming software.
 +
 +All Genesys boards are 100% tested during the manufacturing process. If any device on the Genesys board fails test or is not responding properly, it is likely that damage occurred during transport or during use. Typical damage includes stressed solder joints and contaminants in switches and buttons resulting in intermittent failures. Stressed solder joints can be repaired by reheating and reflowing solder, and contaminants can be cleaned with off-the-shelf electronics cleaning products. If a board fails test within the warranty period, it will be replaced at no cost. If a board fails test outside of the warranty period and cannot be easily repaired, Digilent can repair the board or offer a discounted replacement. Contact Digilent for more details.
 +
 +
 +
 +----