Genesys MIG Tutorial

This page was made to help step through the Genesys MIG wizard and to get an example project running.

Things you will need…

- ISE 14.7 installed on your computer

- Genesys Board from Digilent

- Power adapter for Genesys

- USB to micro USB cable

- Adept 2.0 from Digilent (Or IMPACT included with ISE 14.7)

Open ISE 14.7 and click new project. You don't need to add any files and the device is XC5VLX50T and the package is FF1136. These settings can be seen below.

Click new source → IP → MIG. This will open up the MIG (Memory Interface Generator) wizard. Verify that the correct fpga shows up and click next.

On this page you will want to select Create Design. By default this is selected click next.

This page is for creating a MIG that will also be compatible with different FPGAs. Since this is just an example design, we can leave all of these options blank and click next.

The Genesys has a DDR2 SDRAM. Select this option in the drop down menu.

The DDR2 chip we are working with is a Micron MT4HTF3264HY-667D3. Select SODIMMs under Memory type and MT4HTF3264HY-667 under Memory Part. Data width should be 64. The page should look like this before clicking next.