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genesys:mig [2015/05/27 21:34] – Sam Lowegenesys:mig [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 Do the same thing for the mig.prj located at project_name/ipcore_dir/MIG_name/example_design Do the same thing for the mig.prj located at project_name/ipcore_dir/MIG_name/example_design
  
-Here is the edited user_deign  mig.prj file+Here is the edited user_design  mig.prj file
  
 {{:genesys:mig.zip|}} {{:genesys:mig.zip|}}
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 {{:genesys:migpost0.png?500|}} {{:genesys:migpost0.png?500|}}
  
 +After this completes, open up test.ise located at project_name\ipcore_dir\MIG_name\example_design\par with ISE 14.7.
 +
 +==== Step Five: PLL to DCM ====
 +
 +The MIG now requires a 266.667 Mhz clk, a 133.333 Mhz clk, a 266.667 MHz clk phase shifted by 90 degrees, and a 200 MHz clk. In order to supply the clocks we need to the MIG, a PLL to DCM is needed. Open up the IP core catalog and select PLL to DCM. In the setup, make sure the device is correct then click ok.
 +
 +{{:genesys:migclk0.png?500|}}
 +
 +The next screen select CLKOUTDCM1 in the drop down menu then click next.
 +
 +{{:genesys:migclk1.png?300|}}
 +
 +On this screen, CLKIN1 should be a 200 MHz Differential source. The multiple value should be set to 4 and the divide, 1. Make sure the options match the picture below. 200 * (4/3) = 266.667. In the next window we will divide by 3. Click next.
 +
 +{{:genesys:migclk2_.png?500|}}
 +
 +On this screen set the divide value to be 3 and verify the output clock is 266.667 MHz then click next.
 +
 +{{:genesys:migclk3.png?300|}}
 +
 +ON the next screen enable the CLK90, CLKDV, and the CLKFX pins. Type 266.667 MHz into the input clock frequency. Divide by value should be 2. Compare with the picture below then click next
 +
 +{{:genesys:migclk4.png?500|}}
 +
 +For the next screen we want to use all Global buffers. Click next.
 +
 +On the next screen select Use M and D values. Set them to 3 and 4 respectively to regenerate a 200 MHz clk. Compare with the picture then click next.
 +
 +{{:genesys:migclk5.png?500|}}
 +
 +Then click finish to complete the wizard. 
 +
 +CLK0_OUT -> clk0
 +
 +CLKDV_OUT -> clkdiv0
 +
 +CLKFX_OUT -> clk200
 +
 +CLK90_OUT -> clk90
 +
 +
 +==== The Example Project ====
 +
 +Using these wizards and the example project, here is the working project on the Genesys board. LED1 is tied to Error and should not illuminate. LED 0 should illuminate. The bit file will be found under Genesys_MIG\ipcore_dir\mem\example_design\par. Digilent's Adept software can be used to program the Genesys.
 +
 +{{:genesys:genesys_mig.zip|}}