Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
fmc_hdmi:refmanual [2014/09/26 17:23] – Added picture Joshua Woldstadfmc_hdmi:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
Line 1: Line 1:
 ====== FMC-HDMI Reference Manual ====== ====== FMC-HDMI Reference Manual ======
  
-====== 1 Overview ======+===== Revision History ===== 
 + 
 +Revised September 3, 2014 
 + 
 +This manual applies to REV D of the board. 
 + 
 + 
 +====== Overview ======
  
-{{:fmc_hdmi:fmc-hdmi-obl-1600.png?300 |}} 
  
 The FPGA Mezzanine Card High-Definition Multimedia Interface (FMC-HDMI) peripheral board enables developers to add HDMI input ports to field-programmable gate array (FPGA) based systems. The FMC-HDMI provides a development platform for customers to utilize high-definition image capturing for use with image processing applications. The FPGA Mezzanine Card High-Definition Multimedia Interface (FMC-HDMI) peripheral board enables developers to add HDMI input ports to field-programmable gate array (FPGA) based systems. The FMC-HDMI provides a development platform for customers to utilize high-definition image capturing for use with image processing applications.
  
 +{{:fmc_hdmi:fmc_hdmi-obl-600.png?300 |}}
 +
 +Features include:
  
   * (2x) HDMI Type A Receptacles   * (2x) HDMI Type A Receptacles
Line 16: Line 25:
  
 ---- ----
-====== 2 Functional Description ======+====== 1. Functional Description ======
  
 The FMC-HDMI card contains two HDMI input ports. The first port, HDMI1, contains an ADI ADV7611 Receiver and outputs a decoded, level translated digital video signal to the FMC connector. The second port, HDMI2, contains an ADI AD8195 Buffer and outputs an HDMI-encoded signal to the FMC connector, leaving the system board to decode the signal (either in the FPGA or an external receiver).  The FMC-HDMI card contains two HDMI input ports. The first port, HDMI1, contains an ADI ADV7611 Receiver and outputs a decoded, level translated digital video signal to the FMC connector. The second port, HDMI2, contains an ADI AD8195 Buffer and outputs an HDMI-encoded signal to the FMC connector, leaving the system board to decode the signal (either in the FPGA or an external receiver). 
Line 23: Line 32:
  
  
-==== 2.1    HDMI1:  Analog Devices ADV7611 Receiver ====+===== 1.1.    HDMI1:  Analog Devices ADV7611 Receiver =====
  
 An Analog Devices ADV7611 Receiver decodes the signal on HDMI1. This low power, 165 MHz receiver supports formats up to UXGA 60Hz at 8 bit at 161 MHz. It has been tested at WUXGA (1080p) 60Hz at 148.5 MHz. The receiver provides an audio output port for audio extracted from the HDMI signal in the following formats: I2S, S/PDIF, and Direct Stream Transfer (DST).  It also features an advanced mute controller. An Analog Devices ADV7611 Receiver decodes the signal on HDMI1. This low power, 165 MHz receiver supports formats up to UXGA 60Hz at 8 bit at 161 MHz. It has been tested at WUXGA (1080p) 60Hz at 148.5 MHz. The receiver provides an audio output port for audio extracted from the HDMI signal in the following formats: I2S, S/PDIF, and Direct Stream Transfer (DST).  It also features an advanced mute controller.
Line 60: Line 69:
 There are level translators present on all audio and video signals, which can level shift to 1.8V, 2.5V, and 3.3V. The desired level is set by the VADJ voltage level. There are level translators present on all audio and video signals, which can level shift to 1.8V, 2.5V, and 3.3V. The desired level is set by the VADJ voltage level.
  
-==== 2.2    HDMI2:  Analog Devices AD8195 Buffer ====+===== 1.2.    HDMI2:  Analog Devices AD8195 Buffer =====
  
 The AD8195 is an HDMI buffer with equalized TMDS inputs and optionally pre-emphasized TMDS outputs. The AD8195 includes bidirectional buffering for the DDC bus and bidirectional buffering with integrated pull-up resistors for the CEC bus. The DDC and CEC buffers are powered independently of the TMDS buffers so that DDC/CEC functionality can be maintained when the system is powered off. The AD8195 is an HDMI buffer with equalized TMDS inputs and optionally pre-emphasized TMDS outputs. The AD8195 includes bidirectional buffering for the DDC bus and bidirectional buffering with integrated pull-up resistors for the CEC bus. The DDC and CEC buffers are powered independently of the TMDS buffers so that DDC/CEC functionality can be maintained when the system is powered off.
Line 95: Line 104:
 //Note: For more information on the AD8195, see ADI datasheets available online at http://www.analog.com/AD8195 // //Note: For more information on the AD8195, see ADI datasheets available online at http://www.analog.com/AD8195 //
  
-==== 2.3    FMC Support ====+===== 1.3.  FMC Support =====
  
 The FMC-HDMI uses a Samtec ASP-134604-01 low pin-count male connector as the main connector for digital signals. The board fully conforms to the VITA 57.1 specs. The connector supports the full range of 1.8V-3.3V bank supply voltages (VADJ). The FMC-HDMI uses a Samtec ASP-134604-01 low pin-count male connector as the main connector for digital signals. The board fully conforms to the VITA 57.1 specs. The connector supports the full range of 1.8V-3.3V bank supply voltages (VADJ).
  
 I²C serves as the IPMI EEPROM, providing hardware definition information. For more information, consult the VITA 57.1 specs. I²C serves as the IPMI EEPROM, providing hardware definition information. For more information, consult the VITA 57.1 specs.
 +
 +====== Errata ======
 +
 +Issue #1: The on-board FMC EEPROM contents do not conform to the VITA 57.1 FPGA Mezzanine Card (FMC) Standard and the IPMI Platform Management FRU Information Storage Specifications.
 +
 +Affected systems: Management software that read and rely on FRU data for some functionality.
 +
 +Impact: minor.
 +
 +Solution: Use the published [[https://github.com/Digilent/FMC-HDMI-frufix|FMC-HDMI-frufix]] project, created in Vivado 2016.4 and targeting the Digilent Zedboard, to reprogram the EEPROM with the correct image. The project can also be adapted to any other Xilinx FPGA board available.