https://dev-wiki.digilent.com/ 2026-10-22T18:44:36+00:00 https://dev-wiki.digilent.com/ https://dev-wiki.digilent.com/ttps://dev-wiki.digilent.com/lib/tpl/digilent-tpl/images/favicon.ico text/html 2022-10-04T18:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/getting-started-with-ipi?rev=1664883526&do=diff Getting Started with Vivado and Vitis for Baremetal Software Projects Overview This guide will work you through the process of setting up a project in Vivado and Vitis. A simple hardware design including a processor with several AXI GPIO peripherals connected to buttons and LEDs will be created. This design will then be exported to the Vitis IDE, and a baremetal software project will be created and run which polls the buttons and writes to the LEDs. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/getting-started-with-pmod-ips?rev=1664883526&do=diff Using Digilent Pmod IPs in Vivado and Vitis (Under Construction) Under Construction This guide has only been partially tested in Vivado and Vitis 2020.1. Not all Pmod IPs have been updated for 2020.1. Use at your discretion. No timeline is currently available for when this guide and all Pmod IPs will be updated. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/getting-started-with-vivado?rev=1664883526&do=diff Getting Started with Vivado for Hardware-Only Designs Introduction [The Vivado Start Page] The goal of this guide is to familiarize the reader with the Vivado tools through the “Hello World!” of hardware, blinking an LED. Note: While this guide was originally created using Vivado 2016.4, the workflow described has not substantially changed, and the guide works as described through to Vivado 2020.1, the latest version as of time of writing. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/hierarchical-blocks?rev=1664883526&do=diff Using a Peripheral with a Hierarchical Block in Vivado IPI and Vitis In Vivado, a Hierarchical Block is a block design within a block design. These blocks allow engineers to partition their designs into separate functional groups. This guide steps through the process of adding a pre-existing hierarchical block to a block design, recreating its example software application, and running the design in hardware. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/install-board-files?rev=1664883526&do=diff Install Digilent's Board Files Digilent provides board files for each FPGA development board. These files make it easy to select the correct part when creating a new project and allow for automated configuration of several complicated components (including the Zynq Processing System and Memory Interface Generator) used in many designs. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/install-cable-drivers?rev=1664883526&do=diff Install Cable Drivers (Linux Only) The Xilinx Unified Installer does not install the USB drivers required to recognize an FPGA board on a Linux system. As such, it must be done manually after the tools have been installed. In order to install Linux cable drivers, first navigate to the following directory in a console window: text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/installation?rev=1664883526&do=diff Installing Vivado, Vitis, and Digilent Board Files redirect text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/installing-board-files?rev=1664883526&do=diff Installing Digilent Board Files (Redirect) redirect text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/installing-vivado-and-sdk?rev=1664883526&do=diff Installing Vivado, Xilinx SDK, and Digilent Board Files Introduction This guide will show the process of installing and configuring the Vivado development environment, used for developing projects to run on Digilent FPGAs. In addition to the installation, Vivado will be pointed at Digilent's board support files, which are used to make the process of creating a new project significantly faster. In addition, the board files make it significantly easier to add a variety of peripherals (such as DD… text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/installing-vivado-and-vitis?rev=1664883526&do=diff Installing Vivado, Vitis, and Digilent Board Files Introduction This guide walks through the process of installing and configuring the Vivado and Vitis development environments. These applications are used to develop projects to run on Digilent FPGA Development Boards. In addition to the installation, Digilent's Board Support Files will be installed, which are used to make the process of creating a new project significantly faster. In addition, the board files make it significantly easier to a… text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/labview?rev=1664883526&do=diff Using I/O on Digilent Boards With LabVIEW LINX Toolkit Introduction This guide will walk you through the process of deploying LabVIEW code to Digilent embedded targets for interacting with device peripherals and I/O, including digital, analog, SPI, I2C and UART. The following Digilent boards can be used with this guide: text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/microblaze-adding-ddr?rev=1664883526&do=diff Adding DDR Memory to a Microblaze Design Add the MIG IP When creating a design with DDR, it's best to add the DDR interface first, as it is typically also used to generate the clock or clocks that will be used by the rest of your design. In the Board tab, right click on the DDR interface and select text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/pmod-requirements?rev=1664883526&do=diff Pmod IP Design Requirements The tables below present information on what Pmods and boards are supported by Pmod IPs, as well as additional design requirements for using each Pmod IP. Table of Contents * * * * * Table 1: Platforms Supported text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/start?rev=1664883526&do=diff Guides for Xilinx Tools Guides * Installing Vivado, Vitis, and Digilent Board Files * Walks through installing Vivado and Vitis, the development environments used to create hardware and software applications targeting Digilent FPGA development boards. * Getting Started with Vivado and Vitis for Baremetal Software Projects * Walks through using Vivado and Vitis to create a design in hardware and software that uses a processor to control buttons and LEDs. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/using-github-releases?rev=1664883526&do=diff Using a Digilent FPGA Github Demo's Releases (2020.1) Warning This page is for internal use only. It is intended to be embedded within other wiki pages and does not provide the full context necessary to use these steps Hardware Only Release (Before Programming) text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-add-hierarchy-example?rev=1664883526&do=diff Add Hierarchical Block Source Files to Your Vitis Application Copy all of the files from the selected hierarchical block's sdk_sources folder (in the vivado-library-hierarchies folder), then paste them into the application project's src folder. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-add-pmod-example?rev=1664883526&do=diff Add a Pmod Software Example to an Application Project Pmod IPs provide software examples, as well as the drivers necessary to control the IPs through an AXI interface. The example files can be found in the platform (“_wrapper”) project's hw/drivers/<pmod>/examples text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-ai?rev=1664883526&do=diff text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-build-software?rev=1664883526&do=diff Build a Vitis Application Once an application project has been set up and includes all necessary sources, it should be built. To build the project and all of its dependencies, select the system project in the Assistant pane, and either click the Build text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-create-app?rev=1664883526&do=diff Create a New Application Project With Vitis open, an application project must be created to hold your source files. In creating an application project, a hardware platform will also be created from an XSA file previously exported from Vivado. ---------- text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-create-blinky-software?rev=1664883526&do=diff Create a Main C Source to Control AXI GPIO Peripherals An application needs source files to define its behavior. This step will show how to create a new source file for the application, and provide some example code. In Vitis' Explorer pane, find the application projects text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-create-pmod-app?rev=1664883526&do=diff Create a New Application Project for Pmod Example Software Check the Programming Language for Pmod Software Examples table to determine which programming language the example was written in. ---------- With Vitis open, an application project must be created to hold your source files. In creating an application project, a hardware platform will also be created from an XSA file previously exported from Vivado. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-launch-app?rev=1664883526&do=diff Launch a Vitis Baremetal Software Application First, many applications require that a serial console is connected to the board, so that standard output (from print statements) can be viewed. For this purpose, a serial terminal should be used. Use a serial terminal application to connect to the board's serial port. Unless otherwise stated, Zynq designs use a baud rate of 115200 and Microblaze designs with an AXI UART Lite IP use a baud rate of 9600. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-launch?rev=1664883526&do=diff Launch Vitis Select the dropdown corresponding to your operating system, below. Open Vitis through the start menu or desktop shortcut created during the installation process. source <install_path>/Vitis/2020.1/settings64.sh vitis Note: Regardless of text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vitis-update-hardware-specification?rev=1664883526&do=diff Update an Existing Vitis Platform's Hardware Specification If a hardware design is changed after having created a Vitis application project, several steps must be taken in order to update the Vitis workspace with a newly exported XSA file. The XSA file contains all of the information relevant to Vitis about the hardware platform, and changing a platform project's specification based on this file will automatically load in any changes. This includes adding new drivers for new IP that have been i… text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-gpio?rev=1664883526&do=diff Add GPIO Peripherals to a Block Design This section covers the steps involved in adding a GPIO peripheral to a block design. While an AXI GPIO IP is used, other IPs and interfaces can potentially be added to your design in the same ways. Two methods are presented here, one for each of the two AXI text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-library?rev=1664883526&do=diff Add Digilent's Vivado Library to a Vivado Project First, download and extract the ZIP file. FIXME Since a release commit has not yet been chosen, the above link does not work. The latest sources from the working branch can be downloaded from this link: text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-microblaze?rev=1664883526&do=diff Add a Microblaze Processor to a Block Design The Microblaze soft-core processor IP can be used to instantiate a processor within your FPGA design. This processor can be very useful for controlling and configuring hardware components. This section discusses how you can add a Microblaze processor and several useful components, including UART for standard output and DDR memory support, to your block design. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-processor?rev=1664883526&do=diff Add a Processor to a Block Design The process of adding a processor to your design is very different depending on the processor used. The Microblaze dropdown should be selected only if using a board that does not have a Zynq or Zynq UltraScale+ device. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-xdc?rev=1664883526&do=diff Add a Master XDC File to a Vivado Project If your project doesn't contain the master Xilinx Design Constraint (XDC) file for your board, the dropdown below details how to add it. This file contains the constraints that your board places on designs using it - specific interfaces wired up to specific pins, clock frequencies, and FPGA bank voltages, for some examples. Click the dropdown below for a walkthrough of how to add this file to your project. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-zynq-ultrascale?rev=1664883526&do=diff Add a Zynq UltraScale Processor to a Block Design The Zynq UltraScale+ MPSoC IP represents the non-FPGA components of a Zynq UltraScale chip, referred to as the Processing System, or PS. It must be used in a block design that wants to connect anything to the processor, and to configure PS-side peripherals, clocks, and other settings. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-add-zynq?rev=1664883526&do=diff Add a Zynq Processor to a Block Design The Zynq7 Processing System IP represents the non-FPGA components of a Zynq chip, referred to as the Processing System, or PS. It must be used in a block design that wants to connect anything to the processor, and to configure PS-side peripherals, clocks, and other settings. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-connect-pmod?rev=1664883526&do=diff Add a Pmod IP to a Block Design Use the Add IP () button to add the IP for your Pmod to your block design. Check the Pmod IP Design Requirements page to determine whether your Pmod is supported. Most Pmod IPs support the Pmod that they are named after, however, there are several exceptions - for example, the Pmod text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-create-block-design?rev=1664883526&do=diff Create a Block Design Click the Create Block Design button in the IP Integrator dropdown of Vivado's Flow Navigator pane. A block design provides a visual representation of your hardware design, and can be used to easily connect and configure IP cores. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-create-hdl-wrapper?rev=1664883526&do=diff Create an HDL Wrapper Additionally, an HDL wrapper must be created for the block design. This process translates the block design into a source file that can be read by the Vivado tools, and is used to build the actual design. Open the Sources pane and locate the block design file (.bd) under the text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-export-fixed-platform?rev=1664883526&do=diff Export a Fixed Post-Synthesis Hardware Platform Once the project has been built, the design must be exported from Vivado so that Vitis has access to information about the hardware that a software application is being developed for. This includes the set of IP connected to the processor, their drivers, their addresses, and more. Exporting hardware after the bitstream has been generated allows you to program your board directly from within Vitis. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-generate-bitstream?rev=1664883526&do=diff Build a Vivado Project At this point, the Vivado Project is ready to be built, by running it through Synthesis and Implementation, and finally generating a bitstream. Click the Generate Bitstream button in the Program and Debug section of the Flow Navigator text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-hardware-manager?rev=1664883526&do=diff Programming an FPGA Board through Vivado's Hardware Manager Vivado's Hardware Manager can be opened by clicking on Open Hardware Manager at the bottom of the Flow Navigator pane on the left side of the Vivado window. The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to the text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-launch?rev=1664883526&do=diff Launch Vivado Select the dropdown corresponding to your operating system, below. Open Vivado through the start menu or desktop shortcut created during the installation process. Open a terminal, and change directory (cd) to a folder where log files for your Vivado session can be placed, then run the following commands: text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-manual-address-editor?rev=1664883526&do=diff Edit the Address Map In the unlikely event that Vivado fails to correctly assign addresses to each AXI IP connected to your processor, you may need to manually set their addresses. If this occurs, errors will pop up during validation of the block design, and the bitstream will not be able to be generated. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-new-project?rev=1664883526&do=diff Create a Vivado Project In Vivado's welcome screen, several options are presented: * Create Project: Opens a wizard used to begin creating a Vivado project from scratch, which will be used here. * Open Project: Can be used to open a Vivado project (defined by an XPR file) that has been previously created or downloaded from the internet. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-validate-block-design?rev=1664883526&do=diff Validate a Block Design Before the Vivado project can be built, the block design must be validated. This step runs an automatic check of the block design to see if there are any potential issues with it. Click the Validate Design button () in the Diagram pane's toolbar (or press the F6 key). text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/vivado-xdc-file?rev=1664883526&do=diff What is a Constraints File? When programming an FPGA through software such as Xilinx's Vivado, you need to inform the software what physical pins on the FPGA that you plan on using or connecting to in relation to the HDL code that you wrote to describe the behavior of the FPGA. text/html 2022-10-04T04:38:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://dev-wiki.digilent.com/programmable-logic/guides/xilinx-unified-installer?rev=1664883526&do=diff Install Vivado and Vitis (Xilinx Unified Installer) The Xilinx Unified Installer can be used to install a variety of different Xilinx tools that can be used to design applications for your FPGA development board. Open Xilinx's Downloads page in a new tab. Find the section of the page entitled