<?xml version="1.0" encoding="UTF-8"?>
<!-- generator="FeedCreator 1.8" -->
<?xml-stylesheet href="https://dev-wiki.digilent.com/lib/exe/css.php?s=feed" type="text/css"?>
<rdf:RDF
    xmlns="http://purl.org/rss/1.0/"
    xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
    xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
    xmlns:dc="http://purl.org/dc/elements/1.1/">
    <channel rdf:about="https://dev-wiki.digilent.com/feed.php">
        <title>Digilent Reference learn:software:tutorials:verilog-project-1</title>
        <description></description>
        <link>https://dev-wiki.digilent.com/</link>
        <image rdf:resource="https://dev-wiki.digilent.com/ttps://dev-wiki.digilent.com/lib/tpl/digilent-tpl/images/favicon.ico" />
       <dc:date>2026-10-23T12:13:23+00:00</dc:date>
        <items>
            <rdf:Seq>
                <rdf:li rdf:resource="https://dev-wiki.digilent.com/learn/software/tutorials/verilog-project-1/start?rev=1664883525&amp;do=diff"/>
            </rdf:Seq>
        </items>
    </channel>
    <image rdf:about="https://dev-wiki.digilent.com/ttps://dev-wiki.digilent.com/lib/tpl/digilent-tpl/images/favicon.ico">
        <title>Digilent Reference</title>
        <link>https://dev-wiki.digilent.com/</link>
        <url>https://dev-wiki.digilent.com/ttps://dev-wiki.digilent.com/lib/tpl/digilent-tpl/images/favicon.ico</url>
    </image>
    <item rdf:about="https://dev-wiki.digilent.com/learn/software/tutorials/verilog-project-1/start?rev=1664883525&amp;do=diff">
        <dc:format>text/html</dc:format>
        <dc:date>2022-10-04T11:38:45+00:00</dc:date>
        <dc:creator>Anonymous (anonymous@undisclosed.example.com)</dc:creator>
        <title>Verilog® HDL: Project 1</title>
        <link>https://dev-wiki.digilent.com/learn/software/tutorials/verilog-project-1/start?rev=1664883525&amp;do=diff</link>
        <description>Check out our full list of Verilog based projects!

Verilog® HDL: Project 1

Learning relevant keywords and concepts

Project Overview

The goal of this project is to learn about the components inside of a Verilog project (but not program an FPGA quite yet, that's the next project). If you have not already installed Vivado, you can find a guide to do so</description>
    </item>
</rdf:RDF>
