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dsdb:rm [2016/05/04 05:43] – [16.1 Seven-Segment Display] sbobrowiczdsdb:rm [2022/10/04 11:38] (current) – external edit 127.0.0.1
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- +======= DSDB Reference Manual =======
-====== Overview ======+
  
 {{ :dsdb:dsdb-obl-600.png?nolink&400|}} {{ :dsdb:dsdb-obl-600.png?nolink&400|}}
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 The DSDB is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE/EDK toolset. These toolsets meld FPGA logic design with embedded ARM software development into an easy to use, intuitive design flow. They can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs. The DSDB is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE/EDK toolset. These toolsets meld FPGA logic design with embedded ARM software development into an easy to use, intuitive design flow. They can be used for designing systems of any complexity, from a complete operating system running multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs.
 +
 +{{ :dsdb:dsdb-walk-around.jpg |}}
  
 ---- ----
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 On-board auxiliary buffers and electronic switches control the direction of signals that differ between Source and Sink. These signals are summarized Table 14. On-board auxiliary buffers and electronic switches control the direction of signals that differ between Source and Sink. These signals are summarized Table 14.
  
-|  **Signal**  |  **Role**  |  **Description**                                             |  **Direction (Zynq POW)**  |  **How to control**  | +|  **Signal**  |  **Role**  |  **Description**                                             |  **Direction (Zynq POW)**          |  **How to control**  | 
-|  **HPD**     | Source     | Hot-plug detect; signals the presence of a Sink to a Source  | Input                      | HDMI_OUT_EN = 1      | +|  **HPD**     | Source     | Hot-plug detect; signals the presence of a Sink to a Source  | Input (requires internal pull-up)  | HDMI_OUT_EN = 1      | 
-| :::          | Sink       | :::                                                          | Output                     | HDMI_OUT_EN = 0      | +| :::          | Sink       | :::                                                          | Output                             | HDMI_OUT_EN = 0      | 
-|  **5V0**     | Source     | Auxiliary power for Sink                                     | Output                     | HDMI_OUT_EN = 1      | +|  **5V0**     | Source     | Auxiliary power for Sink                                     | Output                             | HDMI_OUT_EN = 1      | 
-| :::          | Sink       | :::                                                          | Input                      | HDMI_OUT_EN = 0      |+| :::          | Sink       | :::                                                          | Input                              | HDMI_OUT_EN = 0      |
  
 //Table 14. HDMI signal direction in Source and Sink roles. //Table 14. HDMI signal direction in Source and Sink roles.
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 ==== 14.1 LCD Display ==== ==== 14.1 LCD Display ====
  
-The LCD has a ILI6122 timing controller mounted on it which interfaces to the TFT display. The user has access only to certain pins of the controller which enable him to send data to the LCD. In order to access the controller pins the LCD uses a strip connector with the following pin-out.+The LCD has a ILI6122 timing controller mounted on it which interfaces to the TFT display. The user has access only to certain pins of the controller, specifically those which are used to send data to the LCD. In order to access the controller pins the LCD uses a strip connector with the following pin-out.
 ^ Pin      ^ Signal           ^ Description                                                 ^ ^ Pin      ^ Signal           ^ Description                                                 ^
 | 1        | BCK_LED_K        | Back-light LED cathode. Connected to the FP6745 LED driver  | | 1        | BCK_LED_K        | Back-light LED cathode. Connected to the FP6745 LED driver  |
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 //Table 15. LCD control signals// //Table 15. LCD control signals//
  
-In order to facilitate the dimming of the back-light on the LCD, the FP6745 LED driver has been used. The user has direct access to the enable pin of the LED-driver; by driving this pin with a PWM signal the user will obtain a variety of back-light intensities dependent on the duty cycle of the PWM signal. When driving the back-light whit PWM it is highly recommended to choose a PWM frequency above 20 KHz, because this circuit may interfere with the Audio circuit. +In order to facilitate the dimming of the back-light on the LCD, the FP6745 LED driver has been used. The user has direct access to the enable pin of the LED-driver; by driving this pin with a PWM signal the user will obtain a variety of back-light intensities dependent on the duty cycle of the PWM signal. When driving the back-light with PWM it is highly recommended to choose a PWM frequency above 20 KHz, because this circuit may interfere with the Audio circuit. 
-Before starting to use the LCD the DSIP pin must be set to logic high. This pin is an enable pin which allows the user to turn off the display without interrupting the timing and data flow. When sending data to the display the following timing specifications must be respected:+Before starting to use the LCD the DISP pin must be set to logic high. This pin is an enable pin which allows the user to turn off the display without interrupting the timing and data flow. When sending data to the display the following timing specifications must be respected:
  
 **Horizontal** **Horizontal**
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 //Table 18. Touch panel pin-out // //Table 18. Touch panel pin-out //
  
-The addressing mode of the I2C is is on 7 bit, with the slave address being 0111000 in binary and the maximum frequency at which the controller can operate is 400 KHz. Additionally to the  I2C protocol there are two other signals provided by the controller, the REST and the INT signal. In order to reset the touch panel controller the RESET pin has to be driven low for at least 1 ms. The INT signal is an I/O signal which will go low while the panel is being touched, when the FT5x16 is in hibernation the same INT signal must be used in order to wake the controller up. When using the INT signal in order to wake the controller, the low pulse generate for the wake-up sequence must be driven low for 0.5 to 1 ms, the reason for this short period is that the INT port will act as an interrupt output port after the wake-up.+The addressing mode of the I2C is 7 bit, with the slave address being 0111000 in binary and the maximum frequency at which the controller can operate is 400 KHz. In addition to the I2C bus there are two other signals provided by the controller, the RESET and the INT signal. In order to reset the touch panel controller the RESET pin has to be driven low for at least 1 ms. The INT signal is an I/O signal which will go low while the panel is being touched. Also, when the FT5x16 is in hibernation the same INT signal must be used in order to wake the controller up. When using the INT signal in order to wake the controller, the low pulse generate for the wake-up sequence must be driven low for 0.5 to 1 ms. The reason for this short period is that the INT port will act as an interrupt output port after the wake-up.
  
 The following registers can be used in order to obtain a minimal functionality of the touch panel: The following registers can be used in order to obtain a minimal functionality of the touch panel:
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 The DSDB contains a four-digit common anode seven-segment LED display. Each of the four digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Figure 15. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful. The DSDB contains a four-digit common anode seven-segment LED display. Each of the four digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark, as shown in Figure 15. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful.
  
-{{ nexys4-ddr:n4s.png?600 |}} +{{ :basys3-_seven_segment_display.png?600 |}} 
-Figure 15. FIXME -- fix figure label by removing from image and placing in text+//Figure 15. Digit Illumination Patterns//
  
 The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate, as shown in Fig 16. The common anode signals are available as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG. For example, the four “D” cathodes from the four digits are grouped together into a single circuit node called “CD.”  These seven cathode signals are available as inputs to the 4-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted.  The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate, as shown in Fig 16. The common anode signals are available as four “digit enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are connected into seven circuit nodes labeled CA through CG. For example, the four “D” cathodes from the four digits are grouped together into a single circuit node called “CD.”  These seven cathode signals are available as inputs to the 4-digit display. This signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding anode signal is asserted. 
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 {{ :basys3-_seven_segment_display_driving.png?500 |}} {{ :basys3-_seven_segment_display_driving.png?500 |}}
-Figure 16. FIXME -- Fix figure label+//Figure 16. Common Anode Circuit Node//
  
 A scanning display controller circuit can be used to show a four-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession at an update rate that is faster than the human eye can detect. Each digit is illuminated just one-fourth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update, or “refresh”, rate is slowed to around 45Hz, a flicker can be noticed in the display. A scanning display controller circuit can be used to show a four-digit number on this display. This circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating, continuous succession at an update rate that is faster than the human eye can detect. Each digit is illuminated just one-fourth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update, or “refresh”, rate is slowed to around 45Hz, a flicker can be noticed in the display.
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 For each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms, for a refresh frequency of about 1 KHz to 60Hz. For example, in a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be illuminated for 1/4 of the refresh cycle, or 4ms. The controller must drive low the cathodes with the correct pattern when the corresponding anode signal is driven high. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be displayed in digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a “7” will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless succession, the display will show “71” in the first two digits. An example timing diagram for a four-digit controller is shown in Figure 17. For each of the four digits to appear bright and continuously illuminated, all four digits should be driven once every 1 to 16ms, for a refresh frequency of about 1 KHz to 60Hz. For example, in a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be illuminated for 1/4 of the refresh cycle, or 4ms. The controller must drive low the cathodes with the correct pattern when the corresponding anode signal is driven high. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be displayed in digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a “7” will be displayed in digit position 2. If AN0, CB, and CC are driven for 4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless succession, the display will show “71” in the first two digits. An example timing diagram for a four-digit controller is shown in Figure 17.
  
-{{ nexys4-ddr:n4u.png?400 |}} +{{ :basys3-seven_segment_timing_diagram.png?400 |}} 
-Figure 17. FIXME -- fix figure label+//Figure 17. Four digit scanning display controller timing diagram//
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- 
 ====== 17 Audio ====== ====== 17 Audio ======
  
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 | **J11**          | Line In          | Stereo        | Light Blue  | | **J11**          | Line In          | Stereo        | Light Blue  |
  
-//Table FIXME. Analog audio signals//+//Table 24. Analog audio signals//
  
 The digital interface of the SSM2603 is wired to the programmable logic side of the Zynq. Audio data is transferred via the I²S protocol. Configuration is done over an I2C bus. The device address of the SSM2603 is 0011010b. All digital I/O are 3.3V level and connect to a 3.3V-powered FPGA bank. The digital interface of the SSM2603 is wired to the programmable logic side of the Zynq. Audio data is transferred via the I²S protocol. Configuration is done over an I2C bus. The device address of the SSM2603 is 0011010b. All digital I/O are 3.3V level and connect to a 3.3V-powered FPGA bank.
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 | **MCLK**         | Master Clock                  | Output                    | L22           | | **MCLK**         | Master Clock                  | Output                    | L22           |
  
-//Table FIXME. Digital audio signals, with the SSM2603 in default slave mode.//+//Table 25. Digital audio signals, with the SSM2603 in default slave mode.//
  
 The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will be used by the audio codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired sampling rate. The default settings require a master clock of 12.288 Mhz, resulting in a 48 kHz sampling rate. For other frequencies and their respective configuration parameters, consult the SSM2603 datasheet. The audio codec needs to be clocked from the Zynq on the MCLK pin. This master clock will be used by the audio codec to establish the audio sampling frequency. This clock is required to be an integer multiple of the desired sampling rate. The default settings require a master clock of 12.288 Mhz, resulting in a 48 kHz sampling rate. For other frequencies and their respective configuration parameters, consult the SSM2603 datasheet.
  
-The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals is specified in Table FIXME. When configured as master, the direction of BCLK, PBLRC and RECLRC is inverted. In this mode, the codec generates the proper frequencies for these clocks. Digilent recommends that the audio codec be used in slave mode, because this tends to simplify the clocking scheme of the FPGA logic. No matter where are the clocks are generated, PBDAT needs to be driven out and RECDAT sampled in sync with them. The master clock is always driven out of the Zynq. +The codec has two modes: master and slave, with the slave being default. In this mode, the direction of the signals is specified in Table 25. When configured as master, the direction of BCLK, PBLRC and RECLRC is inverted. In this mode, the codec generates the proper frequencies for these clocks. Digilent recommends that the audio codec be used in slave mode, because this tends to simplify the clocking scheme of the FPGA logic. No matter where are the clocks are generated, PBDAT needs to be driven out and RECDAT sampled in sync with them. The master clock is always driven out of the Zynq. 
  
-The timing diagram of an I²S stream can be seen on Figure FIXME. Note the one-cycle delay of the data stream with respect to the left/right clock changing state. Audio samples are transmitted MSB first, noted as 1 in the diagram.+The timing diagram of an I²S stream can be seen on Figure 18. Note the one-cycle delay of the data stream with respect to the left/right clock changing state. Audio samples are transmitted MSB first, noted as 1 in the diagram.
  
 {{ :zybo:aud1.png?500 |}} {{ :zybo:aud1.png?500 |}}
  
-//Figure FIXME. I²S timing diagram.//+//Figure 18. I²S timing diagram.//
  
 The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when not used in the design, it will stay low and the analog outputs of the codec will stay muted. To enable the analog outputs, drive this signal high. It is important to note that the audio codec will not receive or transmit any audio data until the MUTE signal is driven high. The digital mute signal (MUTE) is active-low, with a pull-down resistor. This means that when not used in the design, it will stay low and the analog outputs of the codec will stay muted. To enable the analog outputs, drive this signal high. It is important to note that the audio codec will not receive or transmit any audio data until the MUTE signal is driven high.
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 ====== 20 Pmod Connectors ====== ====== 20 Pmod Connectors ======
  
-Pmod connectors are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V user power supplies (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig. FIXME. The 3.3V user supply is current limited to 0.3A and it is shared between Pmods, digital breadboard and MXP connector (J4). See section **1.2 User Power Supplies** and **1.3 User Power Supplies Monitoring** for a detailed description.+Pmod connectors are 2x6, right-angle, 100-mil spaced female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V user power supplies (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig. 19. The 3.3V user supply is current limited to 0.3A and it is shared between Pmods, digital breadboard and MXP connector (J4). See section **1.2 User Power Supplies** and **1.3 User Power Supplies Monitoring** for a detailed description.
  
-{{ :zybo:pmod1f.png?300 |}} +{{ :basys3-pmod_connector.png?300 |}} 
-FIXME -- Remove figure label from picture and correctly label in text+//Figure 19. Pmod Connecter Front View//
  
 Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information. Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod expansion connectors to add ready-made functions like A/D’s, D/A’s, motor drivers, sensors, and other functions. See www.digilentinc.com for more information.
  
-The DSDB has three Pmod connectors, some of which behave differently than others. Each Pmod connector falls into one of two categories: standard or MIO connected. Table FIXME specifies which category each Pmod falls into, and also lists the Zynq pins they are connected to. +The DSDB has three Pmod connectors, some of which behave differently than others. Each Pmod connector falls into one of two categories: standard or MIO connected. Table 26 specifies which category each Pmod falls into, and also lists the Zynq pins they are connected to. 
  
 | Pmod JA (Standard)  | Pmod JB (Standard)  | Pmod JC (MIO)  | | Pmod JA (Standard)  | Pmod JB (Standard)  | Pmod JC (MIO)  |
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 | JA10: AA8           | JB10: AA4           | JC10: E6       | | JA10: AA8           | JB10: AA4           | JC10: E6       |
  
-//Table FIXME. Pmod pinout//+//Table 26. Pmod pinout//
  
 The following sections describe the differences between the Pmod types. The following sections describe the differences between the Pmod types.
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 {{ :dsdb:mxp-pinout.png |}} {{ :dsdb:mxp-pinout.png |}}
 +//Figure 20. MXP Pins//
  
 ^ Signal Name ^ Reference ^ Direction ^ Description ^ ^ Signal Name ^ Reference ^ Direction ^ Description ^
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 |  UART.TX  |  DGND  |  Output  | UART transmit output. UART lines are electrically identical to DIO lines. | |  UART.TX  |  DGND  |  Output  | UART transmit output. UART lines are electrically identical to DIO lines. |
 |  DGND  |  N/A  |  N/A  | Reference for digital signals, +5 V, and +3.3 V. | |  DGND  |  N/A  |  N/A  | Reference for digital signals, +5 V, and +3.3 V. |
 +//Table 27. MXP Pin Descriptions//
  
 The +3V3 pin is driven by the 3V3_USER of the DSDB, and the +5V pin is driven by the 5V0_USER rail. See section **1 Power Supplies** for information on the characteristics of these power rails. The +3V3 pin is driven by the 3V3_USER of the DSDB, and the +5V pin is driven by the 5V0_USER rail. See section **1 Power Supplies** for information on the characteristics of these power rails.
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 {{ :dsdb:dsdb_breadboard_labels.png |}} {{ :dsdb:dsdb_breadboard_labels.png |}}
-//Figure FIXME. Signal Breadboards with pinout//+//Figure 21. Signal Breadboards with pinout//
  
 Each of the three signal breadboards has different functions described in the following section.  Each of the three signal breadboards has different functions described in the following section.