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dsdb:pg [2016/06/01 22:26] – Sam Kdsdb:pg [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ====== Prerequisites ====== ====== Prerequisites ======
 ===Hardware=== ===Hardware===
-  * **SDB**+  * **DSDB**
 ===Software=== ===Software===
-  * LabVIEW 2015 or newer+  * LabVIEW 2015 SP1 or newer
   * LabVIEW FPGA   * LabVIEW FPGA
   * NI Xilinx Tools   * NI Xilinx Tools
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 **Creating an FPGA Target VI** **Creating an FPGA Target VI**
   - In the **Project Explorer** window, right-click **My Computer** and select **New»Targets and Devices**.   - In the **Project Explorer** window, right-click **My Computer** and select **New»Targets and Devices**.
-  - In the **Add Targets and Devices on My Computer** window, select **New target or device**, expand <wrap todo>ELVIS</wrap>, and highlight <wrap todo>DSDB</wrap>. Click OK. The target is discovered and the target and target properties are loaded into the project tree. +  - In the **Add Targets and Devices on My Computer** window, select **New target or device**, expand **Digilent**, and highlight **Digital Systems Development Board**. Click OK. The target is discovered and the target and target properties are loaded into the project tree. 
-  - In the **Project Explorer** window, right-click <wrap todo>FPGA Target (Board1, DE FPGA Board)</wrap> and select **New»FPGA I/O**. The **New FPGA I/O** window opens. +  - In the **Project Explorer** window, right-click **FPGA Target (DSDB, Digital Systems Development Board)**, and select **New»VI**. A blank VI opens. Select the block diagram window. 
-  - In the Available Resources pane, expand **Slide Switches** and select **SW0**. Click **Add** to move SW0 to the New FPGA I/O pane. This adds this FPGA resource to the project. +  - In the **Project Explorer** window FPGA Target (DSDB, Digital Systems Development Board) tree view, select **SW0** and **LED0** and drag them onto the block diagram as shown in the image below. 
-  - Expand **Push Buttons** and select **BTN0**. Click **Add** to move BTN0 to the New FPGA I/O pane. +{{ :dsdb:dropswo.png?600 |}}
-  - Expand **LEDs** and select **LED0** and **LED2**. Click **Add** to move the LEDs to the New FPGA I/O pane. +
-  - Click **OK**. Notice that the selected FPGA resources were added to the FPGA Target tree in the **Project Explorer** window as shown in <wrap todo>Figure 1.1 </wrap>. +
-  - In the **Project Explorer** window, right-click <wrap todo>FPGA Target (Board1, DE FPGA Board)</wrap>, and select **New»VI**. A blank VI opens. Select the block diagram window. +
-  - In the **Project Explorer** window <wrap todo>FPGA Target (Board1, DE FPGA Board)</wrap> tree view, select **SW0** and **LED0** and drag them onto the block diagram as shown in <wrap todo>Figure 1.1 </wrap>.+
   - In the LabVIEW block diagram, wire SW0 output to the LED0 input.   - In the LabVIEW block diagram, wire SW0 output to the LED0 input.
-  - In the **Project Explorer** window <wrap todo>FPGA Target (Board1, DE FPGA Board)</wrap> tree view, select **BTN0** and **LED2** and drag them onto the block diagram.+  - In the **Project Explorer** window FPGA Target (DSDB, Digital Systems Development Board) tree view, select **BTN0** and **LED2** and drag them onto the block diagram.
   - In the LabVIEW block diagram, wire BTN0 output to the LED2 input.   - In the LabVIEW block diagram, wire BTN0 output to the LED2 input.
   - Add a While Loop around the resources.   - Add a While Loop around the resources.
-  - Wire a false constant to the stop condition of the While Loop. \\ <wrap todo>Figure 1.2</wrap>+  - Wire a false constant to the stop condition of the While Loop as shown below. 
 +{{ :dsdb:blockdiag.png?600 |}}
   - Save the VI as //FPGA_Design.vi//.   - Save the VI as //FPGA_Design.vi//.
  
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   - Open the front panel of FPGA_Design.vi.   - Open the front panel of FPGA_Design.vi.
   - Click the **Run** button to run the VI.   - Click the **Run** button to run the VI.
-  - The application compiles VHDL code and generates a bitstream file that is downloaded into the FPGA configuration storage. The **Generating Intermediate Files** window opens and displays the compilation progress. The **LabVIEW FPGA Compile Server** window opens and runs. The compilation takes several minutes. +  - The application compiles VHDL code and generates a bitstream file that is downloaded into the FPGA configuration storage. The **Generating Intermediate Files** window opens and displays the compilation progress. The **LabVIEW FPGA Compile Server** window opens and runs. Choose compile locally. The compilation takes several minutes. See an image of the compile server window below. 
 +{{ :dsdb:compileserver.png?600 |}} 
   - When the compilation finishes, click the **Stop Server** button to close the LabVIEW FPGA Compile Server.   - When the compilation finishes, click the **Stop Server** button to close the LabVIEW FPGA Compile Server.
-  - Click **OK** in the **Successful Compile Report** window.+  - Click **Close** in the **Successful Compile Report** window as shown in the image below. 
 +{{ :dsdb:compilationsuccess.png?600 |}}
   - The application is running on the FPGA board at this time.   - The application is running on the FPGA board at this time.
   - Move switch SW0 up and down; LED0 should correspondingly light and turn off.   - Move switch SW0 up and down; LED0 should correspondingly light and turn off.
   - Press button BTN0; LED2 should correspondingly light and turn off.   - Press button BTN0; LED2 should correspondingly light and turn off.
 +
 +More DSDB examples can be found in the LabVIEW Example Finder.
 +  - In LabVIEW Click **Help>>Find Examples**.
 +  - Click the **Search** tab.
 +  - Search for 'dsdb'.
 +  - Open one of the provided examples and follow the included instructions.