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| dsdb:pg [2016/06/01 22:12] – Sam K | dsdb:pg [2022/10/04 11:38] (current) – external edit 127.0.0.1 | ||
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| ====== Prerequisites ====== | ====== Prerequisites ====== | ||
| ===Hardware=== | ===Hardware=== | ||
| - | * **SDB** | + | * **DSDB** |
| ===Software=== | ===Software=== | ||
| - | * LabVIEW 2015 or newer | + | * LabVIEW 2015 SP1 or newer |
| * LabVIEW FPGA | * LabVIEW FPGA | ||
| * NI Xilinx Tools | * NI Xilinx Tools | ||
| Line 21: | Line 21: | ||
| **Creating a Project** | **Creating a Project** | ||
| - Launch LabVIEW. | - Launch LabVIEW. | ||
| - | - In the Getting Started window, click Empty Project. The new project opens in the Project Explorer window. | + | - In the **Getting Started** window, click **Empty Project**. The new project opens in the **Project Explorer** window. |
| - | - Save the project as **FPGA_Design.lvproj**. | + | - Save the project as //FPGA_Design.lvproj//. |
| **Creating an FPGA Target VI** | **Creating an FPGA Target VI** | ||
| - | - In the Project Explorer window, right-click My Computer and select New»Targets and Devices. | + | - In the **Project Explorer** window, right-click |
| - | - In the Add Targets and Devices on My Computer window, select New target or device, expand | + | - In the **Add Targets and Devices on My Computer** window, select |
| - | - In the Project Explorer window, right-click | + | - In the **Project Explorer** window, right-click |
| - | - In the Available Resources pane, expand Slide Switches and select SW0. Click Add to move SW0 to the New FPGA I/O pane. This adds this FPGA resource to the project. | + | - In the **Project Explorer** window FPGA Target (DSDB, Digital Systems Development |
| - | - Expand Push Buttons and select BTN0. Click Add to move BTN0 to the New FPGA I/O pane. | + | {{ : |
| - | - Expand LEDs and select LED0 and LED2. Click Add to move the LEDs to the New FPGA I/O pane. | + | |
| - | - Click OK. Notice that the selected FPGA resources were added to the FPGA Target tree in the Project Explorer window as shown in <wrap todo> | + | |
| - | - In the Project Explorer window, right-click <wrap todo> | + | |
| - | - In the Project Explorer window | + | |
| - In the LabVIEW block diagram, wire SW0 output to the LED0 input. | - In the LabVIEW block diagram, wire SW0 output to the LED0 input. | ||
| - | - In the Project Explorer window | + | - In the **Project Explorer** window FPGA Target (DSDB, Digital Systems Development |
| - In the LabVIEW block diagram, wire BTN0 output to the LED2 input. | - In the LabVIEW block diagram, wire BTN0 output to the LED2 input. | ||
| - Add a While Loop around the resources. | - Add a While Loop around the resources. | ||
| - | - Wire a false constant to the stop condition of the While Loop. \\ <wrap todo> | + | - Wire a false constant to the stop condition of the While Loop as shown below. |
| - | - Save the VI as **FPGA_Design.vi**. | + | {{ : |
| + | - Save the VI as //FPGA_Design.vi//. | ||
| **Running the FPGA VI** | **Running the FPGA VI** | ||
| - Verify that the USB cable is connected to the DSDB and host PC, and the power switch is moved to the ON position. | - Verify that the USB cable is connected to the DSDB and host PC, and the power switch is moved to the ON position. | ||
| - Open the front panel of FPGA_Design.vi. | - Open the front panel of FPGA_Design.vi. | ||
| - | - Click the Run button to run the VI. | + | - Click the **Run** button to run the VI. |
| - | - The application compiles VHDL code and generates a bitstream file that is downloaded into the FPGA configuration storage. The Generating Intermediate Files window opens and displays the compilation progress. The LabVIEW FPGA Compile Server window opens and runs. The compilation takes several minutes. | + | - The application compiles VHDL code and generates a bitstream file that is downloaded into the FPGA configuration storage. The **Generating Intermediate Files** window opens and displays the compilation progress. The **LabVIEW FPGA Compile Server** window opens and runs. Choose compile locally. The compilation takes several minutes. |
| - | - When the compilation finishes, click the Stop Server button to close the LabVIEW FPGA Compile Server. | + | {{ : |
| - | - Click OK in the Successful Compile Report window. | + | - When the compilation finishes, click the **Stop Server** button to close the LabVIEW FPGA Compile Server. |
| + | - Click **Close** | ||
| + | {{ : | ||
| - The application is running on the FPGA board at this time. | - The application is running on the FPGA board at this time. | ||
| - Move switch SW0 up and down; LED0 should correspondingly light and turn off. | - Move switch SW0 up and down; LED0 should correspondingly light and turn off. | ||
| - Press button BTN0; LED2 should correspondingly light and turn off. | - Press button BTN0; LED2 should correspondingly light and turn off. | ||
| + | |||
| + | More DSDB examples can be found in the LabVIEW Example Finder. | ||
| + | - In LabVIEW Click **Help>> | ||
| + | - Click the **Search** tab. | ||
| + | - Search for ' | ||
| + | - Open one of the provided examples and follow the included instructions. | ||

