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cmod_a7:refmanual [2016/06/23 23:21] – [Cmod A7 Reference Manual] sbobrowiczcmod_a7:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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 ======= Cmod A7 Reference Manual ======= ======= Cmod A7 Reference Manual =======
 +<WRAP center round important 60%> 
 +The Cmod A7-15T is no longer in production. Once the current stock is depleted, it will be discontinued. 
 +</WRAP>
 {{ :cmod_a7:cmod_a7-obl-600.png?nolink&400|}} {{ :cmod_a7:cmod_a7-obl-600.png?nolink&400|}}
  
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 ^ Clock Management Tiles   | 5                    | 5                    | ^ Clock Management Tiles   | 5                    | 5                    |
  
-The Cmod A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Cmod A7 Resource Center, accessible from reference.digilentinc.com.+The Cmod A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Cmod A7 Resource Center, accessible from [[/start|Digilent Reference]].
  
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 Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written, however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Cmod A7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for Quad-SPI programming. Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written, however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Cmod A7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for Quad-SPI programming.
  
-Quad-SPI programming can be done using the hardware manager in Vivado. +Quad-SPI programming can be done using the hardware manager in Vivado. The [[cmod_a7:pg|Cmod A7 Programming Guide]] walks through the process of doing this.
  
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 //Table 7.1. DIP Pin Voltage Ratings// //Table 7.1. DIP Pin Voltage Ratings//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix 7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet|Artix 7 datasheet]] from Xilinx.
  
 ==== 7.2 Analog Inputs ==== ==== 7.2 Analog Inputs ====
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 //Figure 7.2.1. Analog Input Circuit// //Figure 7.2.1. Analog Input Circuit//
  
-The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf|7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter]]. A demo that uses the XADC core is available on the Cmod A7 resource center.+The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC|7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter]]. A demo that uses the XADC core is available on the Cmod A7 resource center.
  
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