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cmod_a7:refmanual [2016/06/16 23:17] – [7.1 DIP Digital I/O] sbobrowiczcmod_a7:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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-========UNDER CONSTRUCTION======== 
- 
 ======= Cmod A7 Reference Manual ======= ======= Cmod A7 Reference Manual =======
 +<WRAP center round important 60%> 
 +The Cmod A7-15T is no longer in production. Once the current stock is depleted, it will be discontinued. 
 +</WRAP>
 {{ :cmod_a7:cmod_a7-obl-600.png?nolink&400|}} {{ :cmod_a7:cmod_a7-obl-600.png?nolink&400|}}
  
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     * 4MB Quad-SPI Flash     * 4MB Quad-SPI Flash
     * USB-JTAG Programming Circuitry     * USB-JTAG Programming Circuitry
-    * Powered from USB or external 4.5-5.5V supply connected to DIP pins+    * Powered from USB or external 3.3-5.5V supply connected to DIP pins
   * **System Connectivity**    * **System Connectivity** 
     * USB-UART bridge     * USB-UART bridge
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     * 1 RGB LED     * 1 RGB LED
     * 2 Push Buttons     * 2 Push Buttons
-    * 8 Slide Switches 
   * **Expansion Connectors**   * **Expansion Connectors**
     * 48-pin DIP connector with 44 Digital I/O and 2 Analog inputs (0-3.3V)     * 48-pin DIP connector with 44 Digital I/O and 2 Analog inputs (0-3.3V)
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 ^ Clock Management Tiles   | 5                    | 5                    | ^ Clock Management Tiles   | 5                    | 5                    |
  
-The Cmod A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Cmod A7 Resource Center, accessible from reference.digilentinc.com.+The Cmod A7 is fully compatible with the high-performance Vivado ® Design Suite. It is supported under the free WebPACK™ license, so designs can be implemented at no additional cost. This free license includes the ability to create MicroBlaze™ soft-core processor designs. Design resources, example projects, and tutorials are available for download at the Cmod A7 Resource Center, accessible from [[/start|Digilent Reference]].
  
 ---- ----
 ====== 1 Power Supplies ====== ====== 1 Power Supplies ======
  
 +The Cmod A7 uses a Linear Technologies LTC3569 triple output buck power regulator to generate the needed voltages for the onboard components. It is connected as shown in Figure 1.1. The characteristics of the outputs are shown in Table 1.1. 
  
 +{{:cmod_a7:cmoda7_b_power.png?800|}}
 +
 +//Figure 1.1. Cmod A7 Power Supply.//
 +
 +
 +^ Net name  ^ Upstream net name  ^ Power IC Type  ^ Power IC Label  ^ Min/Typ/Max Voltage  ^ Max. Current   ^ Major Devices and Connectors                              ^
 +^ VCC1V0    | VU                 | Switching PS   | IC10            | 0.95V/1.00V/1.05V    | 1.2A           | FPGA Core and Block RAM                                   |
 +^ VCC1V8    | VU                 | Switching PS   | IC10            | 1.71V/1.80V/1.89V    | 0.6A           | FPGA AUX and ADC, USB Core                                |
 +^ VCC3V3    | VU                 | Switching PS   | IC10            | 3.135V/3.30V/3.465V  | 0.6A           | SRAM, USB Controller, PMOD, LEDS, Buttons, FPGA USER I/O  |
 +
 +//Table 1.1. Power Rail Characteristics.//
 +
 +==== 1.1 Power Input Options ====
 +
 +It is possible to power the Cmod A7 from either USB or from an external power supply attached to pins 24 and 25 of the DIP connector, labeled "VU" and GND" respectively. The required characteristics of a power source attached to either of these two options is outlined in Table 1.1.1. 
 +
 +
 +^ Connector Type  ^ Connector Label  ^ Schematic net name  ^ Min/Rec/Max Voltage  ^
 +| USB             | J3               | USB5V0              | 4.5/5/5.5            |
 +| DIP             | J1 (Pin 24)      | VU                  | 3.32/5/5.5           |
 +
 +The minimum external voltage that can be applied to VU depends on the amount of current drawn from the VCC3V3 rail via the Pmod header. With 0mA drawn from the Pmod header the minimum external voltage is 3.32V. With 100mA drawn from the Pmod header the minimum external voltage is 3.38V. With 250mA drawn from the Pmod header the minimum external voltage is 3.48V.
 +
 +When the Cmod A7 is being powered by the USB connector, the voltage from the USB device is driven onto the VU pin. This allows you to power an external circuit from the USB host in addition to the Cmod A7. The VU pin is driven via a schottky diode, so a small voltage drop will occur, but it should be assumed the voltage present on VU will be close to 5V. 
 +
 +**Warning: When a USB host is attached to the micro USB connector, the VU pin on the DIP connector (pin 24) is driven to the voltage being provided by the USB host (typically between 4.5V-5.5V). If you have a power source attached to the VU pin, you must disconnect it before attaching a USB host, or risk damaging it. This can be particularly dangerous if the power source is a battery.**
  
 ---- ----
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 Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written, however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Cmod A7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for Quad-SPI programming. Programming the flash can take as long as four to five minutes, which is mostly due to the lengthy erase process inherent to the memory technology. Once written, however, FPGA configuration can be very fast—less than a second. Bitstream compression, SPI bus width, and configuration rate are factors controlled by the Xilinx tools that can affect configuration speed. The Cmod A7 supports x1, x2, and x4 bus widths and data rates of up to 50 MHz for Quad-SPI programming.
  
-Quad-SPI programming can be done using the hardware manager in Vivado. +Quad-SPI programming can be done using the hardware manager in Vivado. The [[cmod_a7:pg|Cmod A7 Programming Guide]] walks through the process of doing this.
  
 ---- ----
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 Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Micron's datasheet for the flash device to learn how to implement a custom controller. Xilinx's AXI Quad SPI core can be used to read/write the flash in a Microblaze design. Refer to Xilinx's product guide for this core to learn more about using it, or to Micron's datasheet for the flash device to learn how to implement a custom controller.
  
----- +{{ :cmod_a7:cmoda7_b_flash.png?500 |}} 
 +//Figure 4.1. Cmod A7 Quad-SPI Flash//
 ---- ----
 ====== 5 USB-UART Bridge ====== ====== 5 USB-UART Bridge ======
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 **Warning: When a USB host is attached to the micro USB connector, the VU pin on the DIP connector (pin 24) is driven to the voltage being provided by the USB host (typically between 4.5V-5.5V). If you have a power source attached to the VU pin, you must disconnect it before attaching a USB host, or risk damaging it. This can be particularly dangerous if the power source is a battery.** **Warning: When a USB host is attached to the micro USB connector, the VU pin on the DIP connector (pin 24) is driven to the voltage being provided by the USB host (typically between 4.5V-5.5V). If you have a power source attached to the VU pin, you must disconnect it before attaching a USB host, or risk damaging it. This can be particularly dangerous if the power source is a battery.**
 +
 +{{ :cmod_a7:cmoda7_b_uart.png?500 | }}
 +//Figure 5.1. Cmod A7 USB-UART//
  
 ---- ----
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 The Cmod A7 includes a tri-color LED, 2 push buttons and 2 individual LEDs. The push buttons are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. The Cmod A7 includes a tri-color LED, 2 push buttons and 2 individual LEDs. The push buttons are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a push button was inadvertently defined as an output). The two push buttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed.
  
-{{ :arty:arty_gpio.png?500 |}}+{{ :cmod_a7:cmoda7_b_gpio.png?500 |}} 
 +//Figure 6.1. Cmod A7 Basic I/O//
  
 The two individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB-UART traffic. The two individual high-efficiency LEDs are anode-connected to the FPGA via 330-ohm resistors, so they will turn on when a logic high voltage is applied to their respective I/O pin. Additional LEDs that are not user-accessible indicate power-on, FPGA programming status, and USB-UART traffic.
- 
 ====6.1 Tri-Color LED ==== ====6.1 Tri-Color LED ====
  
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 The Cmod A7 has a 48-pin DIP connector for connecting to breadboards and custom fixtures. The pins have 100-mil spacing, and the entire module is .7 inches by 2.75 inches. Of the 48-pins, 44 are connected directly to FPGA Digital I/O's, 2 are voltage-divided and connected to FPGA Analog inputs, and two are connected to power pins. The pin numbering of the DIP connector is shown in figure 7.1. The Cmod A7 has a 48-pin DIP connector for connecting to breadboards and custom fixtures. The pins have 100-mil spacing, and the entire module is .7 inches by 2.75 inches. Of the 48-pins, 44 are connected directly to FPGA Digital I/O's, 2 are voltage-divided and connected to FPGA Analog inputs, and two are connected to power pins. The pin numbering of the DIP connector is shown in figure 7.1.
  
 +{{ :cmod_a7:cmoda7_b_dip.png?direct&200 |}}
 +
 +//Figure 7.1. DIP Pin diagram//
 +
 +VU (pin 24) can be used to power the Cmod A7 when it is not connected to a USB host. When the device is connected to a USB host, VU is driven by the 5V rail of the USB connector and can be used to power devices external to the Cmod A7. See the "Power" section of this manual for more information on powering the Cmod A7. 
 ==== 7.1 DIP Digital I/O ==== ==== 7.1 DIP Digital I/O ====
  
-The pins connected directly to the FPGA can be used as general purpose inputs or outputs. There are no series resistors between the FPGA and the DIP pins, so care should be taken not to cause shorts or connect them to voltages greater allowed by the FPGA. The absolute maximum voltages for these pins are outlined in Table 7.1.+The pins connected directly to the FPGA can be used as general purpose inputs or outputs. There are no series resistors between the FPGA and the DIP pins, so care should be taken not to cause shorts or connect them to voltages greater than allowed by the FPGA. The absolute maximum voltages for these pins are outlined in Table 7.1.
  
  
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 //Table 7.1. DIP Pin Voltage Ratings// //Table 7.1. DIP Pin Voltage Ratings//
  
-For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf|Artix 7 datasheet]] from Xilinx.+For more information on the electrical characteristics of the pins connected to the FPGA, please see the [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet|Artix 7 datasheet]] from Xilinx. 
 + 
 +==== 7.2 Analog Inputs ==== 
 + 
 +Pins 15 and 16 of the DIP connector are used as analog inputs to the XADC module of the FPGA. The FPGA expects that the inputs range from 0-1 V, so we use an external circuit to scale down the input voltage from 3.3V. This circuit is shown in Figure 7.2.1. This circuit allows the XADC module to accurately measure any voltage between 0V and 3.3V (relative to GND on pin 25) that is applied to either of these pins. 
 + 
 +{{ :cmod_a7:cmoda7_b_analog.png?direct&500 |}} 
 + 
 +//Figure 7.2.1. Analog Input Circuit// 
 + 
 +The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. Either channel can be driven by any of the two auxiliary analog inputs connected to the DIP pins. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled [[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC|7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter]]. A demo that uses the XADC core is available on the Cmod A7 resource center.
  
 ---- ----
 +
 ====== 8 Pmod Connector ====== ====== 8 Pmod Connector ======
  
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 The Cmod A7 has one "standard" type Pmod connector, and the FPGA pin connections for it are described in table 8.1. Standard Pmod connectors are connected to the FPGA via 200 Ohm series resistors. The series resistors prevent short circuits that can occur if the user accidentally drives a signal that is supposed to be used as an input. The downside to this added protection is that these resistors can limit the maximum switching speed of the data signals.  The Cmod A7 has one "standard" type Pmod connector, and the FPGA pin connections for it are described in table 8.1. Standard Pmod connectors are connected to the FPGA via 200 Ohm series resistors. The series resistors prevent short circuits that can occur if the user accidentally drives a signal that is supposed to be used as an input. The downside to this added protection is that these resistors can limit the maximum switching speed of the data signals. 
  
-{{ nexys4-ddr:n4v.png?350 |}}+{{ :basys3-pmod_connector.png?350 |}}
 //Figure 8.1. Pmod Diagram// //Figure 8.1. Pmod Diagram//