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anvyl:refmanual [2014/09/11 21:25] – [Flash Memory] Joshua Woldstadanvyl:refmanual [2022/10/04 11:38] (current) – external edit 127.0.0.1
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   * GPIO: 14 LEDs (10 red, 2 yellow, 2 green), 8 slide switches, 8 DIP switches in 2 groups and 4 push buttons   * GPIO: 14 LEDs (10 red, 2 yellow, 2 green), 8 slide switches, 8 DIP switches in 2 groups and 4 push buttons
   * breadboard with 10 Digital I/O’s    * breadboard with 10 Digital I/O’s 
-  * 32 I/O’s routed to 40-pin expansion connector (I/O’s are shared with Pmod connectors) +  * 32 I/O’s routed to 40-pin expansion connector (I/O’s are shared with Pmod ports) 
-  * seven 12-pin Pmod connectors with 56 I/O’s total+  * seven 12-pin Pmod ports with 56 I/O’s total
   * ships with a 20W power supply and USB cable   * ships with a 20W power supply and USB cable
  
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 ====== USB-UART Bridge (Serial Port) ====== ====== USB-UART Bridge (Serial Port) ======
  
-{{ :anvyl:usb1.png?400 |}}+{{ :anvyl:usb1.png?300|}} 
 + 
 +The Anvyl includes an FTDI FT2232HQ USB-UART bridge to allow PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.com under the "Virtual Com Port" or VCP heading, convert USB packets to UART/serial port data. Serial port data is exchanged with the FPGA using a two-wire serial port (TXD/RXD) and software flow control (XON/XOFF). After the drivers are installed, I/O commands from the PC directed to the COM port will produce serial data traffic on the T19 and T20 FPGA pins. 
 + 
 +The FT2232HQ, attached to port J12, is also used as the controller for the Digilent USB-JTAG circuitry, but these two functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with their data, and vice-versa. 
 + 
 +---- 
 + 
 +====== USB HID Hosts ====== 
 + 
 +{{ :anvyl:hid1.png?500|}} 
 + 
 +Two Microchip PIC24FJ128GB106 microcontrollers provide the Anvyl with USB HID host capability. Firmware in the microcontrollers can drive a mouse or a keyboard attached to the type A USB connectors at J13 and J14 labeled "HID" and “HOST”. Hubs are not supported, so only a single mouse or a single keyboard can be used at each port.  
 + 
 +The “HOST” PIC24 drives four signals into the FPGA – two are dedicated as a keyboard/mouse port following the PS/2 protocol, and two are connected to the FPGA’s two-wire serial programming port, so the FPGA can be programmed from a file stored on a USB memory stick. To program the FPGA, attach a FAT formatted memory stick containing a single .bit programming file in the root directory, load JP2, and cycle board power. This will cause the PIC processor to program the FPGA, and any incorrect bit files will automatically be rejected. Note the PIC24 reads the FPGA's mode, init, and done pins, and can drive the PROG pin as a part of the programming sequence. 
 + 
 +==== HID Controller ==== 
 + 
 +To access a USB host controller, EDK designs can use the standard PS/2 core (non-EDK designs can use a simple state machine).   
 + 
 +{{ :anvyl:hid2.png?500 |}} 
 + 
 +Mice and keyboards that use the PS/2 protocol¹  use a two-wire serial bus (clock and data) to communicate with a host device. Both use 11-bit words that include a start, stop, and odd parity bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in the figure. The clock and data signals are only driven when data transfers occur, and otherwise they are held in the idle state at logic ‘1’. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface. 
 + 
 +¹Not all keyboard manufacturers strictly adhere to the PS/2 specifications; some keyboards may not produce the proper signaling voltages or use the standard communication protocols. 
 + 
 +==== Keyboard ==== 
 + 
 +The keyboard uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports). 
 + 
 +PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 (binary “11110000”) key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0 (binary “11100000”) ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host device can also send data to the keyboard. Below is a short list of some common commands a host might send. 
 + 
 +| ED  | Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns FA after receiving ED, then host sends a byte to set LED status: bit 0 sets Scroll Lock, bit 1 sets Num Lock, and bit 2 sets Caps lock. Bits 3 to 7 are ignored.   | 
 +| EE  | Echo (test). Keyboard returns EE after receiving EE.                                                                                                                                                                               | 
 +| F3  | Set scan code repeat rate. Keyboard returns F3 on receiving FA, then host sends second byte to set the repeat rate.                                                                                                                | 
 +| FE  | Resend. FE directs keyboard to re-send most recent scan code.                                                                                                                                                                      | 
 +| FF  | Reset. Resets the keyboard                                                                                                                                                                                                         | 
 + 
 +The keyboard can send data to the host only when both the data and clock lines are high (or idle). Since the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host pulls the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30KHz) when the data is sent, and data is valid on the falling edge of the clock. 
 + 
 +Scan codes for most PS/2 keys are shown in the figure below. 
 + 
 +{{ :anvyl:key1.png?700 |}} 
 + 
 +//Fig. 11. PS/2 keyboard scan codes. 
 +// 
 + 
 +---- 
 + 
 +====== Mouse ====== 
 + 
 +The mouse outputs a clock and data signal when it is moved, otherwise, these signals remain at logic ‘1’. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz.  
 + 
 +The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and Right button presses (a ‘1’ indicates the button is being pressed). 
 + 
 +{{ :anvyl:mou1.png?600 |}} 
 + 
 +//Fig. 12. Mouse navigation bytes.// 
 + 
 +====== Keypad ====== 
 + 
 +The Anvyl keypad has 16 labeled keys (0-F). It is set up as a matrix in which each row of buttons from left to right are tied to a row pin, and each column from top to bottom  
 +is tied to a column pin. This gives the user four row pins and four column pins to address a button push. When a button is pressed, the pins corresponding to that button’s row and column are connected. 
 + 
 +To read a button’s state, the column pin in which the button resides must be driven low while the other three column pins are driven high. This enables all of the buttons in that column. When a button in that column is pushed, the corresponding row pin will read logic low.  
 + 
 +The state of all 16 buttons can be determined in a four-step process by enabling each of the four columns one at a time. This can be accomplished by rotating an “1110” pattern through the column pins. During each step, the logic levels of the row pins correspond to the state of the buttons in that column.  
 + 
 +To allow simultaneous button presses in the same row, instead configure the column pins as bi-directional with internal pull-up resistors and keep the columns not currently being read at high impedance. 
 + 
 +{{ :anvyl:keyp1.png?500|}} 
 + 
 +^ Keypad Pinout       ^^ 
 +| ROW1:          | E4  | 
 +| ROW2:          | F3  | 
 +| ROW3:          | G8  | 
 +| ROW4:          | G7  | 
 +| COL1:          | H8  | 
 +| COL2:          | J7  | 
 +| COL3:          | K8  | 
 +| COL4:          | K7  | 
 + 
 + 
 +//Fig. 13. Keypad schematic 
 +// 
 + 
 +---- 
 + 
 +====== Oscillators/Clocks ====== 
 + 
 +The Anvyl board includes a single 100MHz Crystal oscillator connected to pin D11 (D11 is a GCLK input in bank 0). The input clock can drive any or all of the four clock management tiles in the Spartan-6. Each tile includes two Digital Clock Managers (DCMs) and one Phase-Locked Loop (PLLs).DCMs provide the four phases of the input frequency (0º, 90º, 180º, and 270º), a divided clock that can be the input clock divided by any integer from 2 to 16 or 1.5, 2.5, 3.5... 7.5, and two antiphase clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any integer from 1 to 32. 
 + 
 +PLLs use Voltage Controlled Oscillators (VCOs) that can be programmed to generate frequencies in the 400MHz to 1080MHz range by setting three sets of programmable dividers during FPGA configuration. VCO outputs have eight equally-spaced outputs (0º, 45º, 90º, 135º, 180º, 225º, 270º, and 315º) that can be divided by any integer between 1 and 128. 
 + 
 +---- 
 + 
 +====== Basic I/O ====== 
 + 
 +The Anvyl board includes fourteen LEDs (ten red, two yellow, and two green), eight slide switches, eight DIP switches in two groups, four push buttons, three two-digit seven-segment displays, and a 630 tie-point breadboard with ten digital I/O’s. The push buttons, slide switches and DIP switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The pushbuttons are "momentary" switches that normally generate a low output when they are at rest, and a high output only when they are pressed. Slide switches and DIP switches generate constant high or low inputs depending on their position. The ten digital breadboard I/O’s (BB1 – BB10) are connected directly to the FPGA so that they can easily be incorporated into custom circuits. 
 + 
 +|  //**Push Buttons**//        ||  **//Slide Switches//**       ||  //**DIP Switches**//       ||  **//LEDs//**        ||  **//Breadboard//**         || 
 +| BTN0:                  | E6   | SW0:                     | V5  | DIP8-1:                | G6  | LD0:           | W3   | BB1:                 | AB20  | 
 +| BTN1:                  | D5   | SW1:                     | U4  | DIP8-2:                | G4  | LD1:           | Y4   | BB2:                 | P17   | 
 +| BTN2:                  | A3   | SW2:                     | V3  | DIP8-3:                | F5  | LD2:           | Y1   | BB3:                 | P18   | 
 +| BTN3:                  | AB9  | SW3:                     | P4  | DIP8-4:                | E5  | LD3:           | Y3   | BB4:                 | Y19   | 
 +|                        |      | SW4:                     | R4  | DIP9-1:                | F8  | LD4:           | AB4  | BB5:                 | Y20   | 
 +|                        |      | SW5:                     | P6  | DIP9-2:                | F7  | LD5:           | W1   | BB6:                 | R15   | 
 +|                        |      | SW6:                     | P5  | DIP9-3:                | C4  | LD6:           | AB3  | BB7:                 | R16   | 
 +|                        |      | SW7:                     | P8  | DIP9-4:                | D3  | LD7:           | AA4  | BB8:                 | R17   | 
 +|                        |      |                          |     |                        |     | LD9:           | R7   | BB9:                 | R19   | 
 +|                        |      |                          |     |                        |     | LD10:          | U6   | BB10:                | V19   | 
 +|                        |      |                          |     |                        |     | LD11:          | T8   |                      |       | 
 +|                        |      |                          |     |                        |     | LD12:          | T7   |                      |       | 
 +|                        |      |                          |     |                        |     | LD13:          | W4   |                      |       | 
 +|                        |      |                          |     |                        |     | LD14:          | U8   |                      |       | 
 + 
 + 
 +---- 
 + 
 +====== Seven Segment Displays ====== 
 + 
 +The Anvyl board contains three 2-digit common cathode seven-segment LED displays. Each of the two digits is composed of seven segments arranged in a “figure eight” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be displayed on a digit by illuminating certain LED segments and leaving the others dark. Of these 128 possible patterns, the ten corresponding to the decimal digits are the most useful. 
 + 
 +The common cathode signals are available as six “digit enable” input signals to the three 2-digit displays. The anodes of similar segments on all six digits are connected into seven circuit nodes labeled AA through AG (so, for example, the six “D” anodes from the six digits are grouped together into a single circuit node called “AD”). These seven anode signals are available as inputs to the 2-digit displays. This signal connection scheme creates a multiplexed display, where the anode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding cathode signal is asserted. 
 + 
 +A scanning display controller circuit can be used to show a two-digit number on each display. This circuit drives the cathode signals and corresponding anode patterns of each digit in a repeating, continuous succession, at an update rate that is faster than the human eye response. Each digit is illuminated just one-sixth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update (or “refresh”) rate is slowed to a given point (around 45 hertz), then most people will begin to see the display flicker. 
 + 
 +In order for each of the six digits to appear bright and continuously illuminated, each digit should be driven once every 1 to 16ms (for a refresh frequency of 1KHz to 60Hz). For example, in a 60Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be illuminated for 1/6 of the refresh cycle, or 2.67ms. The controller must assure that the correct anode pattern is present when the corresponding cathode signal is driven. To illustrate the process, if Cat1 is asserted while AB and AC are asserted, then a “1” will be displayed in digit position 1. Then, if Cat2 is asserted while AA, AB and AC are asserted, then a “7” will be displayed in digit position 2. If Cat1 and AB, AC are driven for 8ms, and then Cat2 and AA, AB, AC are driven for 8ms in an endless succession, the display will show “17”. An example timing diagram for a two-digit controller is shown below. 
 + 
 +{{ :anvyl:sev1.png?500 |}} 
 + 
 +//Fig. 14. Seven-segment displays.// 
 + 
 +{{ :anvyl:sev2.png?300 |}} 
 + 
 +====== Expansion Connectors ====== 
 + 
 +The Anvyl board has a 2x20 pin connector and seven 12-pin Pmod ports. Pmod ports are 2x6 right-angle, 100-mil female connectors that work with standard 2x6 pin headers available from a variety of catalog distributors. Each 12-pin Pmod port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals. VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. Digilent produces a large collection of Pmod accessory boards that can attach to the Pmod ports. We have a set of recommended Pmods for the Anvyl called the “Anvyl Pmod Pack”. 
 + 
 +{{ :anvyl:exp1.png?400 |}} 
 + 
 +The 40-pin expansion connector has 32 I/O signals that are shared with Pmods JD, JE, JF and JG. It also provides GND, VCC3V3, and VCC5V0 connections. 
 + 
 +| //**Pmod JA**//         || //**Pmod JB**//         || //**Pmod JC**//         || //**Pmod JD**//         || //**Pmod JE**//        || //**Pmod JF**//        || //**Pmod JG**//        || 
 +| JA1:             | AA18  | JB1:             | Y16   | JC1:             | Y10   | JD1:             | AB13  | JE1:             | U10  | JF1:             | V7   | JG1:             | V20  | 
 +| JA2:             | AA16  | JB2:             | AB14  | JC2:             | AB12  | JD2:             | Y12   | JE2:             | V9   | JF2:             | W6   | JG2:             | T18  | 
 +| JA3:             | Y15   | JB3:             | Y14   | JC3:             | AB11  | JD3:             | T11   | JE3:             | Y8   | JF3:             | Y7   | JG3:             | D17  | 
 +| JA4:             | V15   | JB4:             | U14   | JC4:             | AB10  | JD4:             | W10   | JE4:             | AA8  | JF4:             | AA6  | JG4:             | B18  | 
 +| JA7:             | AB18  | JB7:             | AA14  | JC7:             | AA12  | JD7:             | W12   | JE7:             | U9   | JF7:             | W8   | JG7:             | T17  | 
 +| JA8:             | AB16  | JB8:             | W14   | JC8:             | Y11   | JD8:             | R11   | JE8:             | W9   | JF8:             | Y6   | JG8:             | A17  | 
 +| JA9:             | AB15  | JB9:             | T14   | JC9:             | AA10  | JD9:             | V11   | JE9:             | Y9   | JF9:             | AB7  | JG9:             | C16  | 
 +| JA10:            | W15   | JB10:            | W11   | JC10:            | Y13   | JD10:            | T10   | JE10:            | AB8  | JF10:            | AB6  | JG10:            | A18  | 
 + 
 +//Table 2. Pmod pinout.// 
 + 
 +