Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
add-ons:pcam-5c:reference-manual [2021/05/14 16:07] – ↷ Links adapted because of a move operation Arthur Brownadd-ons:pcam-5c:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1
Line 108: Line 108:
 The Pcam 5C includes a dual-lane MIPI CSI-2 interface that is used to transmit image data from the OV5640 image sensor on the Pcam 5C to the attached host. It consists of three differential pairs, two for data and one for a clock signal, which are all routed to the 15-pin FFC connector. The clock and data signals are driven by the image sensor and should be treated as inputs by the attached host.  The Pcam 5C includes a dual-lane MIPI CSI-2 interface that is used to transmit image data from the OV5640 image sensor on the Pcam 5C to the attached host. It consists of three differential pairs, two for data and one for a clock signal, which are all routed to the 15-pin FFC connector. The clock and data signals are driven by the image sensor and should be treated as inputs by the attached host. 
  
-The physical layer of the MIPI CSI-2 interface is called D-PHY. It is supported by the I/O blocks on Xilinx Ultrascale devices natively, but requires some passive circuitry external to the FPGA in order to be connected to Xilinx 7-series devices. For detailed information on the circuitry required to use D-PHY with a 7-series device, see the [[https://www.xilinx.com/support/documentation/application_notes/xapp894-d-phy-solutions.pdf|XAPP894 Application Note]] available from Xilinx.+The physical layer of the MIPI CSI-2 interface is called D-PHY. It is supported by the I/O blocks on Xilinx Ultrascale devices natively, but requires some passive circuitry external to the FPGA in order to be connected to Xilinx 7-series devices. For detailed information on the circuitry required to use D-PHY with a 7-series device, see the [[https://docs.xilinx.com/v/u/en-US/xapp894-d-phy-solutions|XAPP894 Application Note]] available from Xilinx.
  
 Further information on the details of MIPI CSI-2 and D-PHY are beyond the scope of this document. Digilent provides open source MIPI CSI-2 and D-PHY Vivado IP cores that can be studied to learn more. These IP cores are included in the [[https://github.com/Digilent/vivado-library|Digilent Vivado Library]]. Further information on the details of MIPI CSI-2 and D-PHY are beyond the scope of this document. Digilent provides open source MIPI CSI-2 and D-PHY Vivado IP cores that can be studied to learn more. These IP cores are included in the [[https://github.com/Digilent/vivado-library|Digilent Vivado Library]].