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| add-ons:pcam-5c:reference-manual [2021/05/14 16:04] – ↷ Page moved from reference:add-ons:pcam-5c:reference-manual to add-ons:pcam-5c:reference-manual Arthur Brown | add-ons:pcam-5c:reference-manual [2022/10/04 04:38] (current) – external edit 127.0.0.1 | ||
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| **Note:** //With select boards, Digilent provides vouchers for licenses as an alternative to these open source IP cores.// | **Note:** //With select boards, Digilent provides vouchers for licenses as an alternative to these open source IP cores.// | ||
| - | A full list of demos that support the Pcam 5C on various Digilent FPGA boards can be found in the [[reference:add-ons: | + | A full list of demos that support the Pcam 5C on various Digilent FPGA boards can be found in the [[add-ons: |
| Although the connector on the Pcam 5C is pin compatible with the Raspberry Pi, Digilent has not validated that the two devices work properly together and does not provide software to do so. | Although the connector on the Pcam 5C is pin compatible with the Raspberry Pi, Digilent has not validated that the two devices work properly together and does not provide software to do so. | ||
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| The Pcam 5C includes a dual-lane MIPI CSI-2 interface that is used to transmit image data from the OV5640 image sensor on the Pcam 5C to the attached host. It consists of three differential pairs, two for data and one for a clock signal, which are all routed to the 15-pin FFC connector. The clock and data signals are driven by the image sensor and should be treated as inputs by the attached host. | The Pcam 5C includes a dual-lane MIPI CSI-2 interface that is used to transmit image data from the OV5640 image sensor on the Pcam 5C to the attached host. It consists of three differential pairs, two for data and one for a clock signal, which are all routed to the 15-pin FFC connector. The clock and data signals are driven by the image sensor and should be treated as inputs by the attached host. | ||
| - | The physical layer of the MIPI CSI-2 interface is called D-PHY. It is supported by the I/O blocks on Xilinx Ultrascale devices natively, but requires some passive circuitry external to the FPGA in order to be connected to Xilinx 7-series devices. For detailed information on the circuitry required to use D-PHY with a 7-series device, see the [[https://www.xilinx.com/ | + | The physical layer of the MIPI CSI-2 interface is called D-PHY. It is supported by the I/O blocks on Xilinx Ultrascale devices natively, but requires some passive circuitry external to the FPGA in order to be connected to Xilinx 7-series devices. For detailed information on the circuitry required to use D-PHY with a 7-series device, see the [[https://docs.xilinx.com/ |
| Further information on the details of MIPI CSI-2 and D-PHY are beyond the scope of this document. Digilent provides open source MIPI CSI-2 and D-PHY Vivado IP cores that can be studied to learn more. These IP cores are included in the [[https:// | Further information on the details of MIPI CSI-2 and D-PHY are beyond the scope of this document. Digilent provides open source MIPI CSI-2 and D-PHY Vivado IP cores that can be studied to learn more. These IP cores are included in the [[https:// | ||
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| The schematics of the %%Pcam 5C%% are available {{reference: | The schematics of the %%Pcam 5C%% are available {{reference: | ||
| - | Example code demonstrating how to use the %%Pcam 5C%% can be found on its [[reference:add-ons: | + | Example code demonstrating how to use the %%Pcam 5C%% can be found on its [[add-ons: |
| If you have any questions or comments about the %%Pcam 5C%%, feel free to post them under the appropriate section (" | If you have any questions or comments about the %%Pcam 5C%%, feel free to post them under the appropriate section (" | ||

