# Output products list for <ddr>
_xmsgs\pn_parser.xmsgs
ddr.gise
ddr.veo
ddr.xco
ddr.xise
ddr\datasheet.txt
ddr\ddr.csv
ddr\docs\phy_only_support_readme.txt
ddr\docs\ug586_7Series_MIS.pdf
ddr\example_design\log.txt
ddr\example_design\par\create_ise.bat
ddr\example_design\par\ddr_icon_cg.xco
ddr\example_design\par\ddr_ila_basic_cg.xco
ddr\example_design\par\ddr_ila_rdpath_cg.xco
ddr\example_design\par\ddr_ila_wrpath_cg.xco
ddr\example_design\par\ddr_vio_async_in_sync_out_cg.xco
ddr\example_design\par\ddr_vio_sync_async_out72_cg.xco
ddr\example_design\par\example_top.cpj
ddr\example_design\par\example_top.ucf
ddr\example_design\par\example_top.xdc
ddr\example_design\par\ise_flow.bat
ddr\example_design\par\makeproj.bat
ddr\example_design\par\readme.txt
ddr\example_design\par\rem_files.bat
ddr\example_design\par\rem_files.tcl
ddr\example_design\par\set_ise_prop.tcl
ddr\example_design\par\xst_options.txt
ddr\example_design\rtl\example_top.vhd
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_afifo.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_cmd_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_cmd_prbs_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_data_prbs_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_init_mem_pattern_ctr.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_memc_flow_vcontrol.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_memc_traffic_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_rd_data_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_read_data_path.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_read_posted_fifo.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_s7ven_data_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_tg_prbs_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_tg_status.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_traffic_gen_top.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_vio_init_pattern_bram.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_wr_data_gen.v
ddr\example_design\rtl\traffic_gen\mig_7series_v1_9_write_data_path.v
ddr\example_design\sim\ddr2_model.v
ddr\example_design\sim\ddr2_model_parameters.vh
ddr\example_design\sim\readme.txt
ddr\example_design\sim\sim.do
ddr\example_design\sim\sim_tb_top.v
ddr\example_design\sim\wiredly.v
ddr\example_design\sim\xsim_files.prj
ddr\example_design\sim\xsim_options.tcl
ddr\example_design\sim\xsim_run.bat
ddr\example_design\synth\example_top.lso
ddr\example_design\synth\example_top.prj
ddr\example_design\synth\synplify_pro.tcl
ddr\mig.prj
ddr\user_design\constraints\ddr.ucf
ddr\user_design\constraints\ddr.xdc
ddr\user_design\log.txt
ddr\user_design\rtl\clocking\mig_7series_v1_9_clk_ibuf.v
ddr\user_design\rtl\clocking\mig_7series_v1_9_infrastructure.v
ddr\user_design\rtl\clocking\mig_7series_v1_9_iodelay_ctrl.v
ddr\user_design\rtl\clocking\mig_7series_v1_9_tempmon.v
ddr\user_design\rtl\controller\mig_7series_v1_9_arb_mux.v
ddr\user_design\rtl\controller\mig_7series_v1_9_arb_row_col.v
ddr\user_design\rtl\controller\mig_7series_v1_9_arb_select.v
ddr\user_design\rtl\controller\mig_7series_v1_9_bank_cntrl.v
ddr\user_design\rtl\controller\mig_7series_v1_9_bank_common.v
ddr\user_design\rtl\controller\mig_7series_v1_9_bank_compare.v
ddr\user_design\rtl\controller\mig_7series_v1_9_bank_mach.v
ddr\user_design\rtl\controller\mig_7series_v1_9_bank_queue.v
ddr\user_design\rtl\controller\mig_7series_v1_9_bank_state.v
ddr\user_design\rtl\controller\mig_7series_v1_9_col_mach.v
ddr\user_design\rtl\controller\mig_7series_v1_9_mc.v
ddr\user_design\rtl\controller\mig_7series_v1_9_rank_cntrl.v
ddr\user_design\rtl\controller\mig_7series_v1_9_rank_common.v
ddr\user_design\rtl\controller\mig_7series_v1_9_rank_mach.v
ddr\user_design\rtl\controller\mig_7series_v1_9_round_robin_arb.v
ddr\user_design\rtl\ddr.vhd
ddr\user_design\rtl\ecc\mig_7series_v1_9_ecc_buf.v
ddr\user_design\rtl\ecc\mig_7series_v1_9_ecc_dec_fix.v
ddr\user_design\rtl\ecc\mig_7series_v1_9_ecc_gen.v
ddr\user_design\rtl\ecc\mig_7series_v1_9_ecc_merge_enc.v
ddr\user_design\rtl\ip_top\mig_7series_v1_9_mem_intfc.v
ddr\user_design\rtl\ip_top\mig_7series_v1_9_memc_ui_top_std.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_byte_group_io.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_byte_lane.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_calib_top.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_if_post_fifo.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_mc_phy.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_mc_phy_wrapper.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_of_pre_fifo.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_4lanes.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_dqs_found_cal.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_dqs_found_cal_hr.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_init.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_oclkdelay_cal.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_prbs_rdlvl.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_rdlvl.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_tempmon.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_top.vhd
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_wrcal.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_phy_wrlvl_off_delay.v
ddr\user_design\rtl\phy\mig_7series_v1_9_ddr_prbs_gen.v
ddr\user_design\rtl\ui\mig_7series_v1_9_ui_cmd.v
ddr\user_design\rtl\ui\mig_7series_v1_9_ui_rd_data.v
ddr\user_design\rtl\ui\mig_7series_v1_9_ui_top.v
ddr\user_design\rtl\ui\mig_7series_v1_9_ui_wr_data.v
ddr_flist.txt
ddr_readme.txt
ddr_xmdf.tcl
