Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
date_generatedThu Jun 25 16:52:10 2015 product_versionVivado v2014.2 (64-bit)
build_version932637 os_platformWIN64
registration_id210658864_0_0_152 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a100t
target_packagecsg324 target_speed-1
random_idecbf5bb9f7825bedbf03d828823632b1 project_idd186ba66f65848908c97e04cef89cbba
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=23 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=4 totalimplruns=4

unisim_transformation
pre_unisim_transformation
bufg=7 bufr=1 carry4=382 dsp48e1=41
fdre=4882 fdse=54 gnd=890 ibuf=7
ldce=16 lut1=128 lut2=690 lut3=1191
lut4=310 lut5=194 lut6=294 mmcme2_adv=2
muxf7=6 muxf8=1 obuf=19 ram32m=4
ram32x1d=44 ram64x1s=16 ramb18e1=10 srl16e=891
srlc32e=4272 vcc=238
post_unisim_transformation
bufg=7 bufr=1 carry4=382 dsp48e1=41
fdre=4882 fdse=54 gnd=890 ibuf=7
ldce=16 lut1=128 lut2=690 lut3=1191
lut4=310 lut5=194 lut6=294 mmcme2_adv=2
muxf7=6 muxf8=1 obuf=19 ramb18e1=10
ramd32=112 rams32=8 rams64e=16 srl16e=891
srlc32e=4272 vcc=238

placer
usage
lut=7188 ff=4896 bram36=0 bram18=10
ctrls=95 dsp=41 iob=26 bufg=0
global_clocks=7 pll=0 bufr=1 nets=17223
movable_instances=14249 pins=113281 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=67.484000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=4878 srls_augmented=0
srls_newly_gated=0 srls_total=5140 bram_ports_augmented=10 bram_ports_newly_gated=1
bram_ports_total=20 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
blk_mem_gen_v8_2/1
iptotal=3 x_ipproduct=Vivado 2014.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=1 x_iplanguage=VHDL
c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./ c_interface_type=0
c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=0 c_enable_32bit_address=0
c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4 c_mem_type=1
c_byte_size=9 c_algorithm=1 c_prim_type=1 c_load_init_file=0
c_init_file_name=no_coe_file_loaded c_init_file=blk_mem_gen_0.mem c_use_default_data=0 c_default_data=0
c_has_rsta=0 c_rst_priority_a=CE c_rstram_a=0 c_inita_val=0
c_has_ena=1 c_has_regcea=0 c_use_byte_wea=0 c_wea_width=1
c_write_mode_a=READ_FIRST c_write_width_a=8 c_read_width_a=8 c_write_depth_a=1024
c_read_depth_a=1024 c_addra_width=10 c_has_rstb=0 c_rst_priority_b=CE
c_rstram_b=0 c_initb_val=0 c_has_enb=1 c_has_regceb=0
c_use_byte_web=0 c_web_width=1 c_write_mode_b=READ_FIRST c_write_width_b=8
c_read_width_b=8 c_write_depth_b=1024 c_read_depth_b=1024 c_addrb_width=10
c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=1 c_has_mux_output_regs_a=0 c_has_mux_output_regs_b=0
c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_use_softecc=0
c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0 c_sim_collision_check=ALL
c_common_clk=1 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0 c_disable_warn_bhv_range=0
c_count_36k_bram=0 c_count_18k_bram=1 c_est_power_summary=Estimated Power for IP _ 2.6455500000000001 mW
cic_compiler_v3_0/1
iptotal=1 c_c1=22 c_c2=22 c_c3=22
c_c4=22 c_c5=22 c_c6=0 c_clk_freq=1
c_component_name=cic c_diff_delay=1 c_family=artix7 c_filter_type=1
c_has_aclken=0 c_has_aresetn=0 c_has_dout_tready=0 c_has_rounding=0
c_i1=22 c_i2=22 c_i3=22 c_i4=22
c_i5=22 c_i6=0 c_input_width=2 c_max_rate=16
c_min_rate=16 c_m_axis_data_tdata_width=24 c_m_axis_data_tuser_width=1 c_num_channels=1
c_num_stages=5 c_output_width=22 c_rate=16 c_rate_type=0
c_sample_freq=1 c_s_axis_config_tdata_width=1 c_s_axis_data_tdata_width=8 c_use_dsp=1
c_use_streaming_interface=1 c_xdevicefamily=artix7
clk_wiz_v5_1/1
iptotal=1 component_name=clk_wiz_0 use_phase_alignment=false use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=2
clkin1_period=10.0 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
fir_compiler_v6_3/1
iptotal=1 c_accum_op_path_widths=38 c_accum_path_widths=38 c_channel_pattern=fixed
c_coef_file=[user-defined] c_coef_file_lines=5 c_coef_mem_packing=0 c_coef_memtype=2
c_coef_path_sign=0 c_coef_path_src=0 c_coef_path_widths=15 c_coef_reload=0
c_coef_width=15 c_col_config=1 c_col_mode=1 c_col_pipe_len=4
c_component_name=hb_fir c_config_packet_size=0 c_config_sync_mode=0 c_config_tdata_width=1
c_data_has_tlast=0 c_data_mem_packing=0 c_data_memtype=0 c_data_path_sign=0
c_data_path_src=0 c_data_path_widths=22 c_data_width=22 c_datapath_memtype=2
c_decim_rate=2 c_elaboration_dir=[user-defined] c_ext_mult_cnfg=none c_filter_type=7
c_filts_packed=0 c_has_aclken=0 c_has_aresetn=0 c_has_config_channel=0
c_input_rate=16 c_interp_rate=1 c_ipbuff_memtype=2 c_latency=15
c_m_data_has_tready=1 c_m_data_has_tuser=0 c_m_data_tdata_width=24 c_m_data_tuser_width=1
c_mem_arrangement=1 c_num_channels=1 c_num_filts=1 c_num_madds=1
c_num_reload_slots=1 c_num_taps=15 c_opbuff_memtype=0 c_opt_madds=none
c_optimization=0 c_output_path_widths=22 c_output_rate=32 c_output_width=22
c_oversampling_rate=5 c_reload_tdata_width=1 c_round_mode=1 c_s_data_has_fifo=1
c_s_data_has_tuser=0 c_s_data_tdata_width=24 c_s_data_tuser_width=1 c_symmetry=1
c_xdevicefamily=artix7 c_zero_packing_factor=1
fir_compiler_v6_3/2
iptotal=1 c_accum_op_path_widths=44 c_accum_path_widths=34_33 c_channel_pattern=fixed
c_coef_file=[user-defined] c_coef_file_lines=81 c_coef_mem_packing=0 c_coef_memtype=2
c_coef_path_sign=0_0 c_coef_path_src=0_0 c_coef_path_widths=20_20 c_coef_reload=0
c_coef_width=20 c_col_config=3 c_col_mode=1 c_col_pipe_len=4
c_component_name=lp_fir c_config_packet_size=0 c_config_sync_mode=0 c_config_tdata_width=1
c_data_has_tlast=0 c_data_mem_packing=0 c_data_memtype=0 c_data_path_sign=1_0
c_data_path_src=0_1 c_data_path_widths=11_11 c_data_width=22 c_datapath_memtype=0
c_decim_rate=1 c_elaboration_dir=[user-defined] c_ext_mult_cnfg=0_1_0_11 c_filter_type=0
c_filts_packed=0 c_has_aclken=0 c_has_aresetn=0 c_has_config_channel=0
c_input_rate=32 c_interp_rate=1 c_ipbuff_memtype=0 c_latency=39
c_m_data_has_tready=0 c_m_data_has_tuser=0 c_m_data_tdata_width=24 c_m_data_tuser_width=1
c_mem_arrangement=1 c_num_channels=1 c_num_filts=1 c_num_madds=3
c_num_reload_slots=1 c_num_taps=162 c_opbuff_memtype=0 c_opt_madds=none
c_optimization=0 c_output_path_widths=21 c_output_rate=32 c_output_width=21
c_oversampling_rate=27 c_reload_tdata_width=1 c_round_mode=1 c_s_data_has_fifo=0
c_s_data_has_tuser=0 c_s_data_tdata_width=24 c_s_data_tuser_width=1 c_symmetry=1
c_xdevicefamily=artix7 c_zero_packing_factor=1
mult_gen_v11_2/1
iptotal=8 c_a_type=0 c_a_width=17 c_b_type=0
c_b_value=10000001 c_b_width=15 c_ccm_imp=0 c_ce_overrides_sclr=0
c_has_ce=0 c_has_sclr=0 c_has_zero_detect=0 c_latency=0
c_model_type=0 c_mult_type=1 c_optimize_goal=0 c_out_high=31
c_out_low=0 c_round_output=0 c_round_pt=0 c_verbosity=0
c_xdevicefamily=artix7
xfft_v9_0/1
iptotal=1 x_ipproduct=Vivado 2014.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xfft x_ipversion=9.0 x_ipcorerevision=4 x_iplanguage=VHDL
c_xdevicefamily=artix7 c_s_axis_config_tdata_width=8 c_s_axis_data_tdata_width=16 c_m_axis_data_tdata_width=48
c_m_axis_data_tuser_width=16 c_m_axis_status_tdata_width=1 c_throttle_scheme=1 c_channels=1
c_nfft_max=10 c_arch=3 c_has_nfft=0 c_use_flt_pt=0
c_input_width=8 c_twiddle_width=8 c_output_width=19 c_has_scaling=0
c_has_bfp=0 c_has_rounding=0 c_has_aclken=0 c_has_aresetn=1
c_has_ovflo=0 c_has_natural_input=1 c_has_natural_output=1 c_has_cyclic_prefix=0
c_has_xk_index=1 c_data_mem_type=1 c_twiddle_mem_type=1 c_bram_stages=3
c_reorder_mem_type=1 c_use_hybrid_ram=0 c_optimize_goal=0 c_cmpy_type=1
c_bfly_type=0

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=artix7
die=xc7a100tcsg324-1 package=csg324 speedgrade=-1 version=2014.2
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=4.000000 pct_inputs_defined=14 user_junc_temp=26.5 (C)
ambient_temp=25.0 (C) user_effective_thetaja=4.562757 airflow=250 (LFM) heatsink=medium (Medium Profile)
user_thetasa=4.6 (C/W) board_selection=medium (10"x10") board_layers=12to15 (12 to 15 Layers) user_thetajb=5.7 (C/W)
user_board_temp=25.0 (C) junction_temp=26.5 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 on-chip_power=0.331268 dynamic=0.233330
effective_thetaja=4.6 thetasa=4.6 (C/W) thetajb=5.7 (C/W) off-chip_power=0.000000
clocks=0.021259 logic=0.002552 signals=0.003647 bram=0.012070
mmcm=0.187673 dsp=0.000890 i/o=0.005238 devstatic=0.097938
vccint_voltage=1.000000 vccint_total_current=0.055804 vccint_dynamic_current=0.040111 vccint_static_current=0.015693
vccaux_voltage=1.800000 vccaux_total_current=0.122471 vccaux_dynamic_current=0.104279 vccaux_static_current=0.018191
vcco33_voltage=3.300000 vcco33_total_current=0.005459 vcco33_dynamic_current=0.001459 vcco33_static_current=0.004000
vcco25_voltage=2.500000 vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco18_voltage=1.800000 vcco18_total_current=0.000000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vccaux_io_voltage=0.000000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccbram_voltage=1.000000 vccbram_total_current=0.001003 vccbram_dynamic_current=0.000703 vccbram_static_current=0.000300
mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
vccadc_voltage=1.800000 vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
confidence_level_design_state=High confidence_level_clock_activity=High confidence_level_io_activity=Low confidence_level_internal_activity=Medium
confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=7105 slice_luts_fixed=0 slice_luts_available=63400 slice_luts_util_percentage=11.20
lut_as_logic_used=2200 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=3.47
lut_as_memory_used=4905 lut_as_memory_fixed=0 lut_as_memory_available=19000 lut_as_memory_util_percentage=25.81
lut_as_distributed_ram_used=76 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=4829 lut_as_shift_register_fixed=0
slice_registers_used=4896 slice_registers_fixed=0 slice_registers_available=126800 slice_registers_util_percentage=3.86
register_as_flip_flop_used=4880 register_as_flip_flop_fixed=0 register_as_flip_flop_available=126800 register_as_flip_flop_util_percentage=3.84
register_as_latch_used=16 register_as_latch_fixed=0 register_as_latch_available=126800 register_as_latch_util_percentage=0.01
f7_muxes_used=6 f7_muxes_fixed=0 f7_muxes_available=31700 f7_muxes_util_percentage=0.01
f8_muxes_used=1 f8_muxes_fixed=0 f8_muxes_available=15850 f8_muxes_util_percentage=<0.01
slice_used=2329 slice_fixed=0 slice_available=15850 slice_util_percentage=14.69
slicel_used=883 slicel_fixed=0 slicem_used=1446 slicem_fixed=0
lut_as_logic_used=2200 lut_as_logic_fixed=0 lut_as_logic_available=63400 lut_as_logic_util_percentage=3.47
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=1712 using_o6_output_only_fixed=
using_o5_and_o6_used=488 using_o5_and_o6_fixed= lut_as_memory_used=4905 lut_as_memory_fixed=0
lut_as_memory_available=19000 lut_as_memory_util_percentage=25.81 lut_as_distributed_ram_used=76 lut_as_distributed_ram_fixed=0
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=16 using_o6_output_only_fixed=
using_o5_and_o6_used=60 using_o5_and_o6_fixed= lut_as_shift_register_used=4829 lut_as_shift_register_fixed=0
using_o5_output_only_used=210 using_o5_output_only_fixed= using_o6_output_only_used=4308 using_o6_output_only_fixed=
using_o5_and_o6_used=311 using_o5_and_o6_fixed= lut_flip_flop_pairs_used=7934 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=63400 lut_flip_flop_pairs_util_percentage=12.51 fully_used_lut_ff_pairs_used=2326 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=1039 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=4569 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=95 minimum_number_of_registers_lost_to_control_set_restriction_used=304(Lost)
memory
block_ram_tile_used=5 block_ram_tile_fixed=0 block_ram_tile_available=135 block_ram_tile_util_percentage=3.70
ramb36_fifo*_used=0 ramb36_fifo*_fixed=0 ramb36_fifo*_available=135 ramb36_fifo*_util_percentage=0.00
ramb18_used=10 ramb18_fixed=0 ramb18_available=270 ramb18_util_percentage=3.70
ramb18e1_only_used=10
dsp
dsps_used=41 dsps_fixed=0 dsps_available=240 dsps_util_percentage=17.08
dsp48e1_only_used=41
clocking
bufgctrl_used=7 bufgctrl_fixed=0 bufgctrl_available=32 bufgctrl_util_percentage=21.87
bufio_used=0 bufio_fixed=0 bufio_available=24 bufio_util_percentage=0.00
mmcme2_adv_used=2 mmcme2_adv_fixed=0 mmcme2_adv_available=6 mmcme2_adv_util_percentage=33.33
plle2_adv_used=0 plle2_adv_fixed=0 plle2_adv_available=6 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_fixed=0 bufmrce_available=12 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_fixed=0 bufhce_available=96 bufhce_util_percentage=0.00
bufr_used=1 bufr_fixed=0 bufr_available=24 bufr_util_percentage=4.16
specific_feature
bscane2_used=0 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=0 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_fixed=0 xadc_available=1 xadc_util_percentage=0.00
primitives
fdre_used=4824 fdre_functional_category=Flop & Latch srlc32e_used=4272 srlc32e_functional_category=Distributed Memory
lut3_used=1075 lut3_functional_category=LUT srl16e_used=868 srl16e_functional_category=Distributed Memory
lut2_used=829 lut2_functional_category=LUT carry4_used=382 carry4_functional_category=CarryLogic
lut4_used=306 lut4_functional_category=LUT lut5_used=220 lut5_functional_category=LUT
lut6_used=174 lut6_functional_category=LUT ramd32_used=112 ramd32_functional_category=Distributed Memory
lut1_used=84 lut1_functional_category=LUT fdse_used=54 fdse_functional_category=Flop & Latch
dsp48e1_used=41 dsp48e1_functional_category=Block Arithmetic obuf_used=19 obuf_functional_category=IO
rams64e_used=16 rams64e_functional_category=Distributed Memory ldce_used=16 ldce_functional_category=Flop & Latch
ramb18e1_used=10 ramb18e1_functional_category=Block Memory rams32_used=8 rams32_functional_category=Distributed Memory
ibuf_used=7 ibuf_functional_category=IO bufg_used=7 bufg_functional_category=Clock
muxf7_used=6 muxf7_functional_category=MuxFx mmcme2_adv_used=2 mmcme2_adv_functional_category=Clock
fdce_used=2 fdce_functional_category=Flop & Latch muxf8_used=1 muxf8_functional_category=MuxFx
bufr_used=1 bufr_functional_category=Clock
io_standard
blvds_25=0 lvcmos25=0 lvttl=0 sstl135=0
lvcmos33=1 diff_sstl15=0 hstl_ii=0 diff_mobile_ddr=0
lvcmos18=1 diff_sstl18_ii=0 hstl_i=0 mobile_ddr=0
hsul_12=0 sstl135_r=0 lvcmos12=0 lvcmos15=0
hstl_i_18=0 diff_hsul_12=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=0 sstl15=0 sstl15_r=0 lvds_25=0
diff_hstl_i=0 rsds_25=0 diff_hstl_ii=0 tmds_33=0
diff_hstl_i_18=0 mini_lvds_25=0 diff_hstl_ii_18=0 ppds_25=0
diff_sstl18_i=0 diff_sstl15_r=0 diff_sstl135=0 diff_sstl135_r=0
pci33_3=0

router
usage
lut=7176 ff=4896 bram36=0 bram18=10
ctrls=95 dsp=41 iob=26 bufg=0
global_clocks=7 pll=0 bufr=1 nets=17223
movable_instances=14249 pins=113281 bogomips=0 high_fanout_nets=12
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=10018236 actual_expansions=6871662 router_runtime=50.329000

synthesis
command_line_options
-part=xc7a100tcsg324-1 -name=default::[not_specified] -top=TopNexys4Spectral -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::4
usage
elapsed=00:05:25s memory_peak=1009.063MB memory_gain=825.500MB