Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
date_generatedThu Jul 30 15:07:20 2015 product_versionVivado v2015.2 (64-bit)
build_version1266856 os_platformWIN64
registration_id210714591_1777503789_0_454 tool_flowVivado
betaFALSE route_designTRUE
target_familyartix7 target_devicexc7a200t
target_packagesbg484 target_speed-1
random_idf4fca05a742c5d23a9e22dc9110e8647 project_ida4a0e2282c20480c951a0b513eecc2d9
project_iteration0

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz cpu_speed2494 MHz
total_processors1 system_ram8.000 GB

vivado_usage
project_data
srcsetcount=42 constraintsetcount=4 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Flow_PerfOptimized_High implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1

unisim_transformation
pre_unisim_transformation
and2b1l=14 bscane2=1 bufg=16 bufgctrl=4
bufh=2 bufio=2 bufr=2 carry4=1330
dsp48e1=11 fdce=2628 fdpe=695 fdre=37238
fdse=1222 gnd=1713 gtpe2_channel=2 gtpe2_common=1
ibuf=36 ibufds=5 ibufds_gte2=1 iddr=7
idelayctrl=3 idelaye2=24 in_fifo=2 iobuf=53
iobufds_diff_out_intermdisable=2 iobuf_intermdisable=16 iserdese2=22 lut1=1843
lut2=4792 lut3=5957 lut4=5441 lut5=7035
lut6=13400 lut6_2=104 mmcme2_adv=4 muxf7=905
muxf8=178 obuf=63 obufds=5 obuft=2
obuftds=1 oddr=21 or2l=2 oserdese2=51
out_fifo=4 phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1
phy_control=1 plle2_adv=3 ram32m=199 ram32x1d=90
ram64m=284 ram64x1d=336 ramb18e1=5 ramb36e1=60
srl16e=364 srlc16e=14 srlc32e=200 startupe2=1
vcc=1440 xadc=1
post_unisim_transformation
and2b1l=14 bscane2=1 bufg=16 bufgctrl=4
bufh=2 bufio=2 bufr=2 carry4=1330
dsp48e1=11 fdce=2628 fdpe=695 fdre=37238
fdse=1222 gnd=1713 gtpe2_channel=2 gtpe2_common=1
ibuf=89 ibufds=5 ibufds_gte2=1 ibufds_intermdisable_int=4
ibuf_intermdisable=16 iddr=7 idelayctrl=3 idelaye2=24
inv=3 in_fifo=2 iserdese2=22 lut1=1843
lut2=4792 lut3=5957 lut4=5441 lut5=7139
lut6=13504 mmcme2_adv=4 muxf7=905 muxf8=178
obuf=63 obufds=6 obuft=71 obuftds=5
oddr=21 or2l=2 oserdese2=51 out_fifo=4
phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1 phy_control=1
plle2_adv=3 ramb18e1=5 ramb36e1=60 ramd32=1374
ramd64e=1808 rams32=398 srl16e=364 srlc16e=14
srlc32e=200 startupe2=1 vcc=1440 xadc=1

placer
usage
lut=38978 ff=35093 bram36=60 bram18=5
ctrls=1867 dsp=11 iob=190 bufg=0
global_clocks=15 pll=3 bufr=2 nets=94886
movable_instances=81536 pins=485442 bogomips=0 effort=2
threads=2 placer_timing_driven=1 timing_constraints_exist=1 placer_runtime=282.115000

power_opt_design
usage
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=35077 srls_augmented=0
srls_newly_gated=0 srls_total=578 bram_ports_augmented=3 bram_ports_newly_gated=5
bram_ports_total=130 flow_state=default
command_line_options_spo
-clocks=default::[not_specified] -include_cells=default::[not_specified] -exclude_cells=default::[not_specified] -cell_types=default::all

ip_statistics
IP_Integrator/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=BlockDiagram
x_ipname=bd_0 x_ipversion=1.00.a x_iplanguage=VHDL numblks=2
numreposblks=2 numnonxlnxblks=0 numhierblks=0 maxhierdepth=0
synth_mode=Global
IP_Integrator/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=BlockDiagram
x_ipname=system x_ipversion=1.00.a x_iplanguage=VHDL numblks=86
numreposblks=51 numnonxlnxblks=9 numhierblks=35 maxhierdepth=1
da_board_cnt=1 synth_mode=Global
MDM/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=mdm x_ipversion=3.2 x_ipcorerevision=3 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_jtag_chain=2 c_use_bscan=0
c_use_config_reset=0 c_interconnect=2 c_mb_dbg_ports=1 c_use_uart=0
c_dbg_reg_access=0 c_dbg_mem_access=0 c_use_cross_trigger=0 c_trace_output=0
c_trace_data_width=32 c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90 c_s_axi_addr_width=32
c_s_axi_data_width=32 c_s_axi_aclk_freq_hz=100000000 c_m_axi_addr_width=32 c_m_axi_data_width=32
c_m_axi_thread_id_width=1 c_data_size=32 c_m_axis_data_width=32 c_m_axis_id_width=7
MicroBlaze/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=microblaze x_ipversion=9.5 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_sco=0 c_freq=100000000 c_use_config_reset=0
c_num_sync_ff_clk=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_clk_debug=2 c_num_sync_ff_dbg_clk=1
c_fault_tolerant=0 c_ecc_use_ce_exception=0 c_lockstep_slave=0 c_endianness=1
c_family=artix7 c_data_size=32 c_instance=system_microblaze_0_0 c_avoid_primitives=0
c_area_optimized=0 c_optimization=0 c_interconnect=2 c_base_vectors=0x00000000
c_m_axi_dp_thread_id_width=1 c_m_axi_dp_data_width=32 c_m_axi_dp_addr_width=32 c_m_axi_dp_exclusive_access=0
c_m_axi_d_bus_exception=1 c_m_axi_ip_thread_id_width=1 c_m_axi_ip_data_width=32 c_m_axi_ip_addr_width=32
c_m_axi_i_bus_exception=0 c_d_lmb=1 c_d_axi=1 c_i_lmb=1
c_i_axi=0 c_use_msr_instr=1 c_use_pcmp_instr=1 c_use_barrel=1
c_use_div=1 c_use_hw_mul=1 c_use_fpu=1 c_use_reorder_instr=1
c_unaligned_exceptions=0 c_ill_opcode_exception=0 c_div_zero_exception=0 c_fpu_exception=0
c_fsl_links=0 c_use_extended_fsl_instr=0 c_fsl_exception=0 c_use_stack_protection=0
c_imprecise_exceptions=0 c_use_interrupt=2 c_use_ext_brk=0 c_use_ext_nm_brk=0
c_use_mmu=0 c_mmu_dtlb_size=4 c_mmu_itlb_size=2 c_mmu_tlb_access=3
c_mmu_zones=2 c_mmu_privileged_instr=0 c_use_branch_target_cache=0 c_branch_target_cache_size=0
c_pc_width=32 c_pvr=0 c_pvr_user1=0x00 c_pvr_user2=0x00000000
c_dynamic_bus_sizing=0 c_reset_msr=0x00000000 c_opcode_0x0_illegal=0 c_debug_enabled=1
c_number_of_pc_brk=2 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_debug_event_counters=5
c_debug_latency_counters=1 c_debug_counter_width=32 c_debug_trace_size=8192 c_debug_external_trace=0
c_debug_profile_size=0 c_interrupt_is_edge=0 c_edge_is_positive=1 c_async_interrupt=1
c_m0_axis_data_width=32 c_s0_axis_data_width=32 c_m1_axis_data_width=32 c_s1_axis_data_width=32
c_m2_axis_data_width=32 c_s2_axis_data_width=32 c_m3_axis_data_width=32 c_s3_axis_data_width=32
c_m4_axis_data_width=32 c_s4_axis_data_width=32 c_m5_axis_data_width=32 c_s5_axis_data_width=32
c_m6_axis_data_width=32 c_s6_axis_data_width=32 c_m7_axis_data_width=32 c_s7_axis_data_width=32
c_m8_axis_data_width=32 c_s8_axis_data_width=32 c_m9_axis_data_width=32 c_s9_axis_data_width=32
c_m10_axis_data_width=32 c_s10_axis_data_width=32 c_m11_axis_data_width=32 c_s11_axis_data_width=32
c_m12_axis_data_width=32 c_s12_axis_data_width=32 c_m13_axis_data_width=32 c_s13_axis_data_width=32
c_m14_axis_data_width=32 c_s14_axis_data_width=32 c_m15_axis_data_width=32 c_s15_axis_data_width=32
c_icache_baseaddr=0x80000000 c_icache_highaddr=0x9fffffff c_use_icache=1 c_allow_icache_wr=1
c_addr_tag_bits=16 c_cache_byte_size=8192 c_icache_line_len=8 c_icache_always_used=1
c_icache_streams=0 c_icache_victims=0 c_icache_force_tag_lutram=0 c_icache_data_width=0
c_m_axi_ic_thread_id_width=1 c_m_axi_ic_data_width=32 c_m_axi_ic_addr_width=32 c_m_axi_ic_user_value=31
c_m_axi_ic_awuser_width=5 c_m_axi_ic_aruser_width=5 c_m_axi_ic_wuser_width=1 c_m_axi_ic_ruser_width=1
c_m_axi_ic_buser_width=1 c_dcache_baseaddr=0x80000000 c_dcache_highaddr=0x9fffffff c_use_dcache=1
c_allow_dcache_wr=1 c_dcache_addr_tag=16 c_dcache_byte_size=8192 c_dcache_line_len=8
c_dcache_always_used=1 c_dcache_use_writeback=0 c_dcache_victims=0 c_dcache_force_tag_lutram=0
c_dcache_data_width=0 c_m_axi_dc_thread_id_width=1 c_m_axi_dc_data_width=32 c_m_axi_dc_addr_width=32
c_m_axi_dc_exclusive_access=0 c_m_axi_dc_user_value=31 c_m_axi_dc_awuser_width=5 c_m_axi_dc_aruser_width=5
c_m_axi_dc_wuser_width=1 c_m_axi_dc_ruser_width=1 c_m_axi_dc_buser_width=1
axi_crossbar_v2_1_axi_crossbar/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=1 c_num_master_slots=8
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000044a000000000000040c00000000000004000000000000000400100000000000044a900000000000041c0000000000000404000000000000041200000 c_m_axi_addr_width=0x0000001000000012000000100000001000000010000000100000001000000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x00000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x0000000100000001000000010000000100000001000000010000000100000001
c_m_axi_read_connectivity=0x0000000100000001000000010000000100000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x0000000100000001000000010000000100000001000000010000000100000001 c_m_axi_read_issuing=0x0000000100000001000000010000000100000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x0000000000000000000000000000000000000000000000000000000000000000 c_connectivity_mode=0
axi_crossbar_v2_1_axi_crossbar/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=1 c_num_master_slots=8
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2
c_num_addr_ranges=1 c_m_axi_base_addr=0x00000000408000000000000044a500000000000044a4000000000000400400000000000044a300000000000044a200000000000044a100000000000040030000 c_m_axi_addr_width=0x0000001000000010000000100000001000000010000000100000001000000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x00000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x0000000100000001000000010000000100000001000000010000000100000001
c_m_axi_read_connectivity=0x0000000100000001000000010000000100000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x0000000100000001000000010000000100000001000000010000000100000001 c_m_axi_read_issuing=0x0000000100000001000000010000000100000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x0000000000000000000000000000000000000000000000000000000000000000 c_connectivity_mode=0
axi_crossbar_v2_1_axi_crossbar/3
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=1 c_num_master_slots=5
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000041e000000000000044a7000000000000400500000000000044a600000000000044a80000 c_m_axi_addr_width=0x0000001000000010000000100000001000000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x00000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x0000000100000001000000010000000100000001
c_m_axi_read_connectivity=0x0000000100000001000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x0000000100000001000000010000000100000001 c_m_axi_read_issuing=0x0000000100000001000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x0000000000000000000000000000000000000000 c_connectivity_mode=0
axi_crossbar_v2_1_axi_crossbar/4
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=4 c_num_master_slots=1
c_axi_id_width=2 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=0
c_num_addr_ranges=1 c_m_axi_base_addr=0x0000000080000000 c_m_axi_addr_width=0x0000001d c_s_axi_base_id=0x00000003000000020000000100000000
c_s_axi_thread_id_width=0x00000000000000000000000000000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x00000009
c_m_axi_read_connectivity=0x00000007 c_r_register=0 c_s_axi_single_thread=0x00000000000000000000000000000000 c_s_axi_write_acceptance=0x00000002000000020000000200000008
c_s_axi_read_acceptance=0x00000002000000020000000200000002 c_m_axi_write_issuing=0x00000008 c_m_axi_read_issuing=0x00000008 c_s_axi_arb_priority=0x00000000000000000000000000000000
c_m_axi_secure=0x00000000 c_connectivity_mode=1
axi_crossbar_v2_1_axi_crossbar/5
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_crossbar x_ipversion=2.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_num_slave_slots=1 c_num_master_slots=3
c_axi_id_width=1 c_axi_addr_width=32 c_axi_data_width=32 c_axi_protocol=2
c_num_addr_ranges=7 c_m_axi_base_addr=0x0000000044a900000000000044a000000000000041c0000000000000412000000000000040c0000000000000404000000000000040000000ffffffffffffffffffffffffffffffffffffffffffffffff0000000044a800000000000044a600000000000041e000000000000040050000ffffffffffffffff0000000044a400000000000044a200000000000044a10000000000004080000000000000400400000000000040030000 c_m_axi_addr_width=0x000000100000001000000010000000100000001200000010000000110000000000000000000000000000001000000011000000100000001000000000000000110000001100000010000000100000001000000010 c_s_axi_base_id=0x00000000
c_s_axi_thread_id_width=0x00000000 c_axi_supports_user_signals=0 c_axi_awuser_width=1 c_axi_aruser_width=1
c_axi_wuser_width=1 c_axi_ruser_width=1 c_axi_buser_width=1 c_m_axi_write_connectivity=0x000000010000000100000001
c_m_axi_read_connectivity=0x000000010000000100000001 c_r_register=1 c_s_axi_single_thread=0x00000001 c_s_axi_write_acceptance=0x00000001
c_s_axi_read_acceptance=0x00000001 c_m_axi_write_issuing=0x000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001 c_s_axi_arb_priority=0x00000000
c_m_axi_secure=0x000000000000000000000000 c_connectivity_mode=0
axi_dma/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_dma x_ipversion=7.1 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_s_axi_lite_addr_width=10 c_s_axi_lite_data_width=32 c_dlytmr_resolution=125
c_prmry_is_aclk_async=0 c_enable_multi_channel=0 c_num_mm2s_channels=1 c_num_s2mm_channels=1
c_include_sg=0 c_sg_include_stscntrl_strm=0 c_sg_use_stsapp_length=0 c_sg_length_width=23
c_m_axi_sg_addr_width=32 c_m_axi_sg_data_width=32 c_m_axis_mm2s_cntrl_tdata_width=32 c_s_axis_s2mm_sts_tdata_width=32
c_micro_dma=0 c_include_mm2s=1 c_include_mm2s_sf=1 c_mm2s_burst_size=256
c_m_axi_mm2s_addr_width=32 c_m_axi_mm2s_data_width=32 c_m_axis_mm2s_tdata_width=32 c_include_mm2s_dre=0
c_include_s2mm=1 c_include_s2mm_sf=1 c_s2mm_burst_size=256 c_m_axi_s2mm_addr_width=32
c_m_axi_s2mm_data_width=32 c_s_axis_s2mm_tdata_width=32 c_include_s2mm_dre=0 c_family=artix7
axi_ethernet_buffer_v2_0/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_ethernet_buffer x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_txmem=4096 c_temac_addr_width=12
c_rxmem=4096 c_txcsum=0 c_rxcsum=0 c_phyaddr=1
c_avb=0 c_stats=1 c_phy_type=3 c_type=1
c_txvlan_tran=0 c_rxvlan_tran=0 c_txvlan_tag=0 c_rxvlan_tag=0
c_txvlan_strp=0 c_rxvlan_strp=0 c_mcast_extend=0 c_enable_lvds=0
c_simulation=0
axi_fifo_mm_s/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_fifo_mm_s x_ipversion=4.1 x_ipcorerevision=2 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_id_width=4 c_s_axi_addr_width=32
c_s_axi_data_width=32 c_s_axi4_data_width=32 c_tx_fifo_depth=4096 c_rx_fifo_depth=4096
c_tx_fifo_pf_threshold=4000 c_tx_fifo_pe_threshold=10 c_rx_fifo_pf_threshold=4000 c_rx_fifo_pe_threshold=10
c_use_tx_cut_through=0 c_data_interface_type=0 c_baseaddr=0x44A00000 c_highaddr=0x44A0FFFF
c_axi4_baseaddr=0x80001000 c_axi4_highaddr=0x80002FFF c_has_axis_tid=0 c_has_axis_tdest=0
c_has_axis_tuser=0 c_has_axis_tstrb=0 c_has_axis_tkeep=1 c_axis_tid_width=4
c_axis_tdest_width=4 c_axis_tuser_width=4 c_use_rx_cut_through=0 c_use_tx_data=1
c_use_tx_ctrl=1 c_use_rx_data=1
axi_gpio/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=4 c_gpio2_width=32 c_all_inputs=0 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=16 c_gpio2_width=16 c_all_inputs=0 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=1 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/3
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=1 c_gpio2_width=32 c_all_inputs=1 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=0 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=0 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/4
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=13 c_gpio2_width=8 c_all_inputs=1 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=1 c_interrupt_present=1 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=1 c_dout_default_2=0x00000000 c_tri_default_2=0xFFFFFFFF
axi_gpio/5
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_gpio x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_gpio_width=3 c_gpio2_width=2 c_all_inputs=0 c_all_inputs_2=0
c_all_outputs=0 c_all_outputs_2=0 c_interrupt_present=1 c_dout_default=0x00000000
c_tri_default=0xFFFFFFFF c_is_dual=1 c_dout_default_2=0x00000000 c_tri_default_2=0x00000000
axi_iic/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_iic x_ipversion=2.0 x_ipcorerevision=8 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_iic_freq=100000 c_ten_bit_adr=0 c_gpo_width=1 c_s_axi_aclk_freq_hz=100000000
c_scl_inertial_delay=0 c_sda_inertial_delay=0 c_sda_level=1 c_smbus_pmbus_host=0
c_default_value=0x00
axi_intc/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_intc x_ipversion=4.1 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_instance=axi_intc_inst c_s_axi_addr_width=9
c_s_axi_data_width=32 c_num_intr_inputs=15 c_num_sw_intr=0 c_kind_of_intr=0xffff9020
c_kind_of_edge=0xffffffff c_kind_of_lvl=0xffffffef c_async_intr=0xFFFF8858 c_num_sync_ff=2
c_ivar_reset_value=0x00000010 c_enable_async=0 c_has_ipr=1 c_has_sie=1
c_has_cie=1 c_has_ivr=1 c_has_ilr=0 c_irq_is_level=1
c_irq_active=0x1 c_disable_synchronizers=1 c_mb_clk_not_connected=1 c_has_fast=1
c_en_cascade_mode=0 c_cascade_master=0
axi_quad_spi/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_quad_spi x_ipversion=3.2 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED async_clk=0 c_family=artix7 c_sub_family=artix7
c_instance=axi_quad_spi_inst c_spi_mem_addr_bits=24 c_type_of_axi4_interface=0 c_xip_mode=0
c_fifo_depth=256 c_sck_ratio=2 c_num_ss_bits=1 c_num_transfer_bits=8
c_spi_mode=2 c_use_startup=1 c_spi_memory=3 c_s_axi_addr_width=7
c_s_axi_data_width=32 c_s_axi4_addr_width=24 c_s_axi4_data_width=32 c_s_axi4_id_width=1
c_s_axi4_baseaddr=0xFFFFFFFF c_s_axi4_highaddr=0x00000000
axi_quad_spi/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_quad_spi x_ipversion=3.2 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED async_clk=0 c_family=artix7 c_sub_family=artix7
c_instance=axi_quad_spi_inst c_spi_mem_addr_bits=24 c_type_of_axi4_interface=0 c_xip_mode=0
c_fifo_depth=256 c_sck_ratio=96 c_num_ss_bits=1 c_num_transfer_bits=8
c_spi_mode=0 c_use_startup=0 c_spi_memory=1 c_s_axi_addr_width=7
c_s_axi_data_width=32 c_s_axi4_addr_width=24 c_s_axi4_data_width=32 c_s_axi4_id_width=1
c_s_axi4_baseaddr=0xFFFFFFFF c_s_axi4_highaddr=0x00000000
axi_timer/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_timer x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_count_width=32 c_one_timer_only=0
c_trig0_assert=1 c_trig1_assert=1 c_gen0_assert=1 c_gen1_assert=1
c_s_axi_data_width=32 c_s_axi_addr_width=5
axi_uart16550/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_uart16550 x_ipversion=2.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=13
c_s_axi_data_width=32 c_is_a_16550=1 c_has_external_xin=0 c_has_external_rclk=0
c_external_xin_clk_hz=25000000
bd_0/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=axi_ethernet x_ipversion=7.0 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED x_iplicense=eth_avb_endpoint@2015.04(design_linking) x_iplicense=tri_mode_eth_mac@2015.04(hardware_evaluation)
blk_mem_gen_v8_2/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=blk_mem_gen x_ipversion=8.2 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_xdevicefamily=artix7 c_elaboration_dir=./
c_interface_type=0 c_axi_type=1 c_axi_slave_type=0 c_use_bram_block=1
c_enable_32bit_address=1 c_ctrl_ecc_algo=NONE c_has_axi_id=0 c_axi_id_width=4
c_mem_type=2 c_byte_size=8 c_algorithm=1 c_prim_type=1
c_load_init_file=0 c_init_file_name=no_coe_file_loaded c_init_file=system_lmb_bram_0.mem c_use_default_data=0
c_default_data=0 c_has_rsta=1 c_rst_priority_a=CE c_rstram_a=0
c_inita_val=0 c_has_ena=1 c_has_regcea=0 c_use_byte_wea=1
c_wea_width=4 c_write_mode_a=WRITE_FIRST c_write_width_a=32 c_read_width_a=32
c_write_depth_a=32768 c_read_depth_a=32768 c_addra_width=32 c_has_rstb=1
c_rst_priority_b=CE c_rstram_b=0 c_initb_val=0 c_has_enb=1
c_has_regceb=0 c_use_byte_web=1 c_web_width=4 c_write_mode_b=WRITE_FIRST
c_write_width_b=32 c_read_width_b=32 c_write_depth_b=32768 c_read_depth_b=32768
c_addrb_width=32 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_mux_pipeline_stages=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0
c_use_softecc=0 c_use_ecc=0 c_en_ecc_pipe=0 c_has_injecterr=0
c_sim_collision_check=ALL c_common_clk=0 c_disable_warn_bhv_coll=0 c_en_sleep_pin=0
c_use_uram=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_deepsleep_pin=0
c_en_shutdown_pin=0 c_disable_warn_bhv_range=0 c_count_36k_bram=32 c_count_18k_bram=0
c_est_power_summary=Estimated Power for IP _ 20.388 mW
clk_wiz_v5_1/1
iptotal=1 component_name=system_clk_wiz_0_0 use_phase_alignment=true use_min_o_jitter=false
use_max_i_jitter=false use_dyn_phase_shift=false use_inclk_switchover=false use_dyn_reconfig=false
enable_axi=0 feedback_source=FDBK_AUTO primitive=MMCM num_out_clk=2
clkin1_period=5.0 clkin2_period=10.0 use_power_down=false use_reset=true
use_locked=true use_inclk_stopped=false feedback_type=SINGLE clock_mgr_type=NA
manual_override=false
fifo_generator_v12_0/1
iptotal=2 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=fifo_generator x_ipversion=12.0 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_common_clock=0 c_count_type=0 c_data_count_width=12
c_default_value=BlankString c_din_width=24 c_dout_rst_val=0 c_dout_width=24
c_enable_rlocs=0 c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0
c_has_almost_full=0 c_has_backup=0 c_has_data_count=0 c_has_int_clk=0
c_has_meminit_file=0 c_has_overflow=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_srst=0 c_has_underflow=0 c_has_valid=0
c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0 c_implementation_type=2
c_init_wr_pntr_val=0 c_memory_type=1 c_mif_file_name=BlankString c_optimization_mode=0
c_overflow_low=0 c_preload_latency=1 c_preload_regs=0 c_prim_fifo_type=4kx9
c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_full_thresh_assert_val=4093
c_prog_full_thresh_negate_val=4092 c_prog_full_type=0 c_rd_data_count_width=12 c_rd_depth=4096
c_rd_freq=1 c_rd_pntr_width=12 c_underflow_low=0 c_use_dout_rst=1
c_use_ecc=0 c_use_embedded_reg=0 c_use_pipeline_reg=0 c_power_saving_mode=0
c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0 c_wr_ack_low=0
c_wr_data_count_width=12 c_wr_depth=4096 c_wr_freq=1 c_wr_pntr_width=12
c_wr_response_latency=1 c_msgon_val=1 c_enable_rst_sync=1 c_error_injection_type=0
c_synchronizer_stage=2 c_interface_type=0 c_axi_type=1 c_has_axi_wr_channel=1
c_has_axi_rd_channel=1 c_has_slave_ce=0 c_has_master_ce=0 c_add_ngc_constraint=0
c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0 c_axi_id_width=1
c_axi_addr_width=32 c_axi_data_width=64 c_axi_len_width=8 c_axi_lock_width=1
c_has_axi_id=0 c_has_axi_awuser=0 c_has_axi_wuser=0 c_has_axi_buser=0
c_has_axi_aruser=0 c_has_axi_ruser=0 c_axi_aruser_width=1 c_axi_awuser_width=1
c_axi_wuser_width=1 c_axi_buser_width=1 c_axi_ruser_width=1 c_has_axis_tdata=1
c_has_axis_tid=0 c_has_axis_tdest=0 c_has_axis_tuser=1 c_has_axis_tready=1
c_has_axis_tlast=0 c_has_axis_tstrb=0 c_has_axis_tkeep=0 c_axis_tdata_width=8
c_axis_tid_width=1 c_axis_tdest_width=1 c_axis_tuser_width=4 c_axis_tstrb_width=1
c_axis_tkeep_width=1 c_wach_type=0 c_wdch_type=0 c_wrch_type=0
c_rach_type=0 c_rdch_type=0 c_axis_type=0 c_implementation_type_wach=1
c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_axis=1 c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0
c_application_type_rach=0 c_application_type_rdch=0 c_application_type_axis=0 c_prim_fifo_type_wach=512x36
c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36 c_prim_fifo_type_rach=512x36 c_prim_fifo_type_rdch=1kx36
c_prim_fifo_type_axis=1kx18 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_ecc_rach=0 c_use_ecc_rdch=0 c_use_ecc_axis=0 c_error_injection_type_wach=0
c_error_injection_type_wdch=0 c_error_injection_type_wrch=0 c_error_injection_type_rach=0 c_error_injection_type_rdch=0
c_error_injection_type_axis=0 c_din_width_wach=32 c_din_width_wdch=64 c_din_width_wrch=2
c_din_width_rach=32 c_din_width_rdch=64 c_din_width_axis=1 c_wr_depth_wach=16
c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_axis=1024 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10 c_wr_pntr_width_axis=10 c_has_data_counts_wach=0
c_has_data_counts_wdch=0 c_has_data_counts_wrch=0 c_has_data_counts_rach=0 c_has_data_counts_rdch=0
c_has_data_counts_axis=0 c_has_prog_flags_wach=0 c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0
c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_axis=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_axis=0 c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023
c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_axis=1023 c_prog_empty_type_wach=0
c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_axis=0 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_axis=1022 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_axis=0
fifo_generator_v12_0/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=fifo_generator x_ipversion=12.0 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_common_clock=0 c_count_type=0 c_data_count_width=4
c_default_value=BlankString c_din_width=4 c_dout_rst_val=0 c_dout_width=4
c_enable_rlocs=0 c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0
c_has_almost_full=0 c_has_backup=0 c_has_data_count=0 c_has_int_clk=0
c_has_meminit_file=0 c_has_overflow=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_srst=0 c_has_underflow=0 c_has_valid=0
c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0 c_implementation_type=2
c_init_wr_pntr_val=0 c_memory_type=1 c_mif_file_name=BlankString c_optimization_mode=0
c_overflow_low=0 c_preload_latency=1 c_preload_regs=0 c_prim_fifo_type=512x36
c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_negate_val=3 c_prog_empty_type=0 c_prog_full_thresh_assert_val=13
c_prog_full_thresh_negate_val=12 c_prog_full_type=0 c_rd_data_count_width=4 c_rd_depth=16
c_rd_freq=1 c_rd_pntr_width=4 c_underflow_low=0 c_use_dout_rst=1
c_use_ecc=0 c_use_embedded_reg=0 c_use_pipeline_reg=0 c_power_saving_mode=0
c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0 c_wr_ack_low=0
c_wr_data_count_width=4 c_wr_depth=16 c_wr_freq=1 c_wr_pntr_width=4
c_wr_response_latency=1 c_msgon_val=1 c_enable_rst_sync=1 c_error_injection_type=0
c_synchronizer_stage=2 c_interface_type=0 c_axi_type=1 c_has_axi_wr_channel=1
c_has_axi_rd_channel=1 c_has_slave_ce=0 c_has_master_ce=0 c_add_ngc_constraint=0
c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0 c_axi_id_width=1
c_axi_addr_width=32 c_axi_data_width=64 c_axi_len_width=8 c_axi_lock_width=1
c_has_axi_id=0 c_has_axi_awuser=0 c_has_axi_wuser=0 c_has_axi_buser=0
c_has_axi_aruser=0 c_has_axi_ruser=0 c_axi_aruser_width=1 c_axi_awuser_width=1
c_axi_wuser_width=1 c_axi_buser_width=1 c_axi_ruser_width=1 c_has_axis_tdata=1
c_has_axis_tid=0 c_has_axis_tdest=0 c_has_axis_tuser=1 c_has_axis_tready=1
c_has_axis_tlast=0 c_has_axis_tstrb=0 c_has_axis_tkeep=0 c_axis_tdata_width=8
c_axis_tid_width=1 c_axis_tdest_width=1 c_axis_tuser_width=4 c_axis_tstrb_width=1
c_axis_tkeep_width=1 c_wach_type=0 c_wdch_type=0 c_wrch_type=0
c_rach_type=0 c_rdch_type=0 c_axis_type=0 c_implementation_type_wach=1
c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_axis=1 c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0
c_application_type_rach=0 c_application_type_rdch=0 c_application_type_axis=0 c_prim_fifo_type_wach=512x36
c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36 c_prim_fifo_type_rach=512x36 c_prim_fifo_type_rdch=1kx36
c_prim_fifo_type_axis=1kx18 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_ecc_rach=0 c_use_ecc_rdch=0 c_use_ecc_axis=0 c_error_injection_type_wach=0
c_error_injection_type_wdch=0 c_error_injection_type_wrch=0 c_error_injection_type_rach=0 c_error_injection_type_rdch=0
c_error_injection_type_axis=0 c_din_width_wach=32 c_din_width_wdch=64 c_din_width_wrch=2
c_din_width_rach=32 c_din_width_rdch=64 c_din_width_axis=1 c_wr_depth_wach=16
c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_axis=1024 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10 c_wr_pntr_width_axis=10 c_has_data_counts_wach=0
c_has_data_counts_wdch=0 c_has_data_counts_wrch=0 c_has_data_counts_rach=0 c_has_data_counts_rdch=0
c_has_data_counts_axis=0 c_has_prog_flags_wach=0 c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0
c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_axis=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_axis=0 c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023
c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_axis=1023 c_prog_empty_type_wach=0
c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_axis=0 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_axis=1022 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_axis=0
fifo_generator_v12_0/3
iptotal=4 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=fifo_generator x_ipversion=12.0 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_common_clock=0 c_count_type=0 c_data_count_width=4
c_default_value=BlankString c_din_width=27 c_dout_rst_val=0 c_dout_width=27
c_enable_rlocs=0 c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0
c_has_almost_full=0 c_has_backup=0 c_has_data_count=0 c_has_int_clk=0
c_has_meminit_file=0 c_has_overflow=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_srst=0 c_has_underflow=0 c_has_valid=0
c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0 c_implementation_type=2
c_init_wr_pntr_val=0 c_memory_type=2 c_mif_file_name=BlankString c_optimization_mode=0
c_overflow_low=0 c_preload_latency=0 c_preload_regs=1 c_prim_fifo_type=512x36
c_prog_empty_thresh_assert_val=8 c_prog_empty_thresh_negate_val=9 c_prog_empty_type=1 c_prog_full_thresh_assert_val=15
c_prog_full_thresh_negate_val=14 c_prog_full_type=0 c_rd_data_count_width=4 c_rd_depth=16
c_rd_freq=1 c_rd_pntr_width=4 c_underflow_low=0 c_use_dout_rst=1
c_use_ecc=0 c_use_embedded_reg=0 c_use_pipeline_reg=0 c_power_saving_mode=0
c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_valid_low=0 c_wr_ack_low=0
c_wr_data_count_width=4 c_wr_depth=16 c_wr_freq=1 c_wr_pntr_width=4
c_wr_response_latency=1 c_msgon_val=1 c_enable_rst_sync=1 c_error_injection_type=0
c_synchronizer_stage=2 c_interface_type=0 c_axi_type=1 c_has_axi_wr_channel=1
c_has_axi_rd_channel=1 c_has_slave_ce=0 c_has_master_ce=0 c_add_ngc_constraint=0
c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0 c_axi_id_width=1
c_axi_addr_width=32 c_axi_data_width=64 c_axi_len_width=8 c_axi_lock_width=1
c_has_axi_id=0 c_has_axi_awuser=0 c_has_axi_wuser=0 c_has_axi_buser=0
c_has_axi_aruser=0 c_has_axi_ruser=0 c_axi_aruser_width=1 c_axi_awuser_width=1
c_axi_wuser_width=1 c_axi_buser_width=1 c_axi_ruser_width=1 c_has_axis_tdata=1
c_has_axis_tid=0 c_has_axis_tdest=0 c_has_axis_tuser=1 c_has_axis_tready=1
c_has_axis_tlast=0 c_has_axis_tstrb=0 c_has_axis_tkeep=0 c_axis_tdata_width=8
c_axis_tid_width=1 c_axis_tdest_width=1 c_axis_tuser_width=4 c_axis_tstrb_width=1
c_axis_tkeep_width=1 c_wach_type=0 c_wdch_type=0 c_wrch_type=0
c_rach_type=0 c_rdch_type=0 c_axis_type=0 c_implementation_type_wach=1
c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_axis=1 c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0
c_application_type_rach=0 c_application_type_rdch=0 c_application_type_axis=0 c_prim_fifo_type_wach=512x36
c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36 c_prim_fifo_type_rach=512x36 c_prim_fifo_type_rdch=1kx36
c_prim_fifo_type_axis=1kx18 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_ecc_rach=0 c_use_ecc_rdch=0 c_use_ecc_axis=0 c_error_injection_type_wach=0
c_error_injection_type_wdch=0 c_error_injection_type_wrch=0 c_error_injection_type_rach=0 c_error_injection_type_rdch=0
c_error_injection_type_axis=0 c_din_width_wach=32 c_din_width_wdch=64 c_din_width_wrch=2
c_din_width_rach=32 c_din_width_rdch=64 c_din_width_axis=1 c_wr_depth_wach=16
c_wr_depth_wdch=1024 c_wr_depth_wrch=16 c_wr_depth_rach=16 c_wr_depth_rdch=1024
c_wr_depth_axis=1024 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_pntr_width_rach=4 c_wr_pntr_width_rdch=10 c_wr_pntr_width_axis=10 c_has_data_counts_wach=0
c_has_data_counts_wdch=0 c_has_data_counts_wrch=0 c_has_data_counts_rach=0 c_has_data_counts_rdch=0
c_has_data_counts_axis=0 c_has_prog_flags_wach=0 c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0
c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_axis=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0
c_prog_full_type_axis=0 c_prog_full_thresh_assert_val_wach=1023 c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023
c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_axis=1023 c_prog_empty_type_wach=0
c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_axis=0 c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022
c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022 c_prog_empty_thresh_assert_val_axis=1022 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0
c_reg_slice_mode_axis=0
gtwizard_v2_5/1
iptotal=1 protocol_file=display_port
lmb_bram_if_cntlr/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_highaddr=0x0001FFFF c_baseaddr=0x00000000
c_num_lmb=1 c_mask=0xc0000000 c_mask1=0x00800000 c_mask2=0x00800000
c_mask3=0x00800000 c_lmb_awidth=32 c_lmb_dwidth=32 c_ecc=0
c_interconnect=0 c_fault_inject=0 c_ce_failing_registers=0 c_ue_failing_registers=0
c_ecc_status_registers=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ce_counter_width=0
c_write_access=2 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_bram_if_cntlr/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_bram_if_cntlr x_ipversion=4.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_highaddr=0x0001FFFF c_baseaddr=0x00000000
c_num_lmb=1 c_mask=0x80000000 c_mask1=0x00800000 c_mask2=0x00800000
c_mask3=0x00800000 c_lmb_awidth=32 c_lmb_dwidth=32 c_ecc=0
c_interconnect=0 c_fault_inject=0 c_ce_failing_registers=0 c_ue_failing_registers=0
c_ecc_status_registers=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ce_counter_width=0
c_write_access=2 c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32
lmb_v10/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32
c_ext_reset_high=1
lmb_v10/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=lmb_v10 x_ipversion=3.0 x_ipcorerevision=6 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_lmb_num_slaves=1 c_lmb_dwidth=32 c_lmb_awidth=32
c_ext_reset_high=1
mig_7series_v2_3/1
iptotal=1 language=Verilog synthesis_tool=Vivado level=CONTROLLER
axi_enable=1 no_of_controllers=1 interface_type=DDR3 axi_enable=1
clk_period=2500 phy_ratio=4 clkin_period=10000 vccaux_io=1.8V
memory_type=COMP memory_part=mt41k256m16xx-125 dq_width=16 ecc=OFF
data_mask=1 ordering=NORM burst_mode=8 burst_type=SEQ
ca_mirror=OFF output_drv=HIGH use_cs_port=0 use_odt_port=1
rtt_nom=40 memory_address_map=BANK_ROW_COLUMN refclk_freq=200 debug_port=OFF
internal_vref=1 sysclk_type=SINGLE_ENDED refclk_type=NO_BUFFER
proc_sys_reset/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=proc_sys_reset x_ipversion=5.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_family=artix7 c_ext_rst_width=4 c_aux_rst_width=4
c_ext_reset_high=1 c_aux_reset_high=0 c_num_bus_rst=1 c_num_perp_rst=1
c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
system_displayport_0_0_dport_wrapper/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=displayport x_ipversion=6.0 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED x_iplicense=displayport@2015.04(hardware_evaluation) c_component_name=system_displayport_0_0 c_family=artix7
c_device=xc7a200t c_flow_direction=0 c_gt_datawidth=2 c_lane_count=2
c_include_hdcp=0 c_secondary_support=0 c_audio_channels=2 c_ieee_oui=000A35
c_vendor_specific=0 c_protocol_selection=0 c_link_rate=10 c_mst_enable=0
c_number_of_mst_streams=2 c_max_bits_per_color=8 c_quad_pixel_enable=0 c_dual_pixel_enable=0
c_ycrcb_enable=0 c_yonly_enable=0 c_buf_bypass=0 c_edp_en=0
tri_mode_ethernet_mac_v9_0/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=tri_mode_ethernet_mac x_ipversion=9.0 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED x_iplicense=eth_avb_endpoint@2015.04(design_linking) x_iplicense=tri_mode_eth_mac@2015.04(hardware_evaluation) c_component_name=bd_0_eth_mac_0
c_physical_interface=RGMII c_half_duplex=false c_has_host=true c_has_mdio=true
c_mdio_external=false c_axilite_freq=150.00 c_add_filter=true c_at_entries=4
c_family=artix7 c_mac_speed=TRI_SPEED c_has_stats=true c_num_stats=34
c_cntr_rst=false c_stats_width=64 c_avb=false c_1588=0
c_tx_tuser_width=1 c_rx_vec_width=79 c_tx_vec_width=79 c_addr_width=12
c_pfc=false c_data_rate=1_Gbps
v_axi4s_vid_out_v3_0_axi4s_vid_out_top/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=v_axi4s_vid_out x_ipversion=3.0 x_ipcorerevision=7 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_s_axis_video_data_width=8 c_s_axis_video_format=2 vid_out_data_width=24
c_s_axis_video_tdata_width=24 ram_addr_bits=5 hysteresis_level=12 fill_guardband=3
vtg_master_slave=1
v_tc/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=v_tc x_ipversion=6.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_has_axi4_lite=1 c_has_intc_if=1 c_gen_interlaced=0
c_gen_hactive_size=1280 c_gen_vactive_size=1024 c_gen_cparity=0 c_gen_fieldid_polarity=1
c_gen_vblank_polarity=1 c_gen_hblank_polarity=1 c_gen_vsync_polarity=1 c_gen_hsync_polarity=1
c_gen_avideo_polarity=1 c_gen_achroma_polarity=1 c_gen_video_format=2 c_gen_hframe_size=1688
c_gen_f0_vframe_size=1066 c_gen_f1_vframe_size=1066 c_gen_hsync_start=1328 c_gen_hsync_end=1440
c_gen_f0_vblank_hstart=1280 c_gen_f0_vblank_hend=1280 c_gen_f0_vsync_vstart=1024 c_gen_f0_vsync_vend=1027
c_gen_f0_vsync_hstart=1280 c_gen_f0_vsync_hend=1280 c_gen_f1_vblank_hstart=1280 c_gen_f1_vblank_hend=1280
c_gen_f1_vsync_vstart=1024 c_gen_f1_vsync_vend=1027 c_gen_f1_vsync_hstart=1280 c_gen_f1_vsync_hend=1280
c_fsync_hstart0=0 c_fsync_vstart0=0 c_fsync_hstart1=0 c_fsync_vstart1=0
c_fsync_hstart2=0 c_fsync_vstart2=0 c_fsync_hstart3=0 c_fsync_vstart3=0
c_fsync_hstart4=0 c_fsync_vstart4=0 c_fsync_hstart5=0 c_fsync_vstart5=0
c_fsync_hstart6=0 c_fsync_vstart6=0 c_fsync_hstart7=0 c_fsync_vstart7=0
c_fsync_hstart8=0 c_fsync_vstart8=0 c_fsync_hstart9=0 c_fsync_vstart9=0
c_fsync_hstart10=0 c_fsync_vstart10=0 c_fsync_hstart11=0 c_fsync_vstart11=0
c_fsync_hstart12=0 c_fsync_vstart12=0 c_fsync_hstart13=0 c_fsync_vstart13=0
c_fsync_hstart14=0 c_fsync_vstart14=0 c_fsync_hstart15=0 c_fsync_vstart15=0
c_max_pixels=4096 c_max_lines=4096 c_num_fsyncs=1 c_interlace_en=0
c_gen_auto_switch=0 c_detect_en=1 c_sync_en=0 c_generate_en=0
c_det_hsync_en=1 c_det_vsync_en=1 c_det_hblank_en=0 c_det_vblank_en=0
c_det_avideo_en=1 c_det_achroma_en=0 c_gen_hsync_en=1 c_gen_vsync_en=1
c_gen_hblank_en=1 c_gen_vblank_en=1 c_gen_avideo_en=1 c_gen_achroma_en=0
c_gen_fieldid_en=0 c_det_fieldid_en=0
v_tc/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=v_tc x_ipversion=6.1 x_ipcorerevision=5 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_has_axi4_lite=0 c_has_intc_if=0 c_gen_interlaced=0
c_gen_hactive_size=1280 c_gen_vactive_size=1024 c_gen_cparity=0 c_gen_fieldid_polarity=1
c_gen_vblank_polarity=1 c_gen_hblank_polarity=1 c_gen_vsync_polarity=1 c_gen_hsync_polarity=1
c_gen_avideo_polarity=1 c_gen_achroma_polarity=1 c_gen_video_format=2 c_gen_hframe_size=1688
c_gen_f0_vframe_size=1066 c_gen_f1_vframe_size=1066 c_gen_hsync_start=1328 c_gen_hsync_end=1440
c_gen_f0_vblank_hstart=1280 c_gen_f0_vblank_hend=1280 c_gen_f0_vsync_vstart=1024 c_gen_f0_vsync_vend=1027
c_gen_f0_vsync_hstart=1280 c_gen_f0_vsync_hend=1280 c_gen_f1_vblank_hstart=1280 c_gen_f1_vblank_hend=1280
c_gen_f1_vsync_vstart=1024 c_gen_f1_vsync_vend=1027 c_gen_f1_vsync_hstart=1280 c_gen_f1_vsync_hend=1280
c_fsync_hstart0=0 c_fsync_vstart0=0 c_fsync_hstart1=0 c_fsync_vstart1=0
c_fsync_hstart2=0 c_fsync_vstart2=0 c_fsync_hstart3=0 c_fsync_vstart3=0
c_fsync_hstart4=0 c_fsync_vstart4=0 c_fsync_hstart5=0 c_fsync_vstart5=0
c_fsync_hstart6=0 c_fsync_vstart6=0 c_fsync_hstart7=0 c_fsync_vstart7=0
c_fsync_hstart8=0 c_fsync_vstart8=0 c_fsync_hstart9=0 c_fsync_vstart9=0
c_fsync_hstart10=0 c_fsync_vstart10=0 c_fsync_hstart11=0 c_fsync_vstart11=0
c_fsync_hstart12=0 c_fsync_vstart12=0 c_fsync_hstart13=0 c_fsync_vstart13=0
c_fsync_hstart14=0 c_fsync_vstart14=0 c_fsync_hstart15=0 c_fsync_vstart15=0
c_max_pixels=4096 c_max_lines=4096 c_num_fsyncs=1 c_interlace_en=0
c_gen_auto_switch=0 c_detect_en=0 c_sync_en=0 c_generate_en=1
c_det_hsync_en=1 c_det_vsync_en=1 c_det_hblank_en=1 c_det_vblank_en=1
c_det_avideo_en=1 c_det_achroma_en=0 c_gen_hsync_en=1 c_gen_vsync_en=1
c_gen_hblank_en=1 c_gen_vblank_en=1 c_gen_avideo_en=1 c_gen_achroma_en=0
c_gen_fieldid_en=0 c_det_fieldid_en=0
v_tpg/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=v_tpg x_ipversion=6.0 x_ipcorerevision=4 x_iplanguage=VHDL
x_ipsimlanguage=MIXED c_s_axis_video_data_width=8 c_m_axis_video_data_width=8 c_s_axis_video_tdata_width=16
c_m_axis_video_tdata_width=24 c_s_axis_video_format=0 c_m_axis_video_format=2 c_s_axis_video_tuser_width=0
c_m_axis_video_tuser_width=1 c_s_axi_addr_width=9 c_s_axi_data_width=32 c_s_axi_clk_freq_hz=100000000
c_active_rows=1080 c_active_cols=1920 c_pattern_control=4110 c_motion_speed=1
c_cross_hairs=6553700 c_zplate_hor_control=30 c_zplate_ver_control=1 c_box_size=50
c_box_color=0 c_stuck_pixel_thresh=0 c_noise_gain=0 c_bayer_phase=4
c_has_intc_if=0 c_has_axi4_lite=1 c_has_vtiming=0
xadc_wiz_v3_1/1
iptotal=1 component_name=system_xadc_wiz_0_0 enable_axi=true enable_axi4stream=false
dclk_frequency=100 enable_busy=true enable_convst=false enable_convstclk=false
enable_dclk=true enable_drp=false enable_eoc=true enable_eos=true
enable_vbram_alaram=false enable_vccddro_alaram=false enable_vccint_alaram=true enable_vccaux_alaram=trueenable_vccpaux_alaram=false
enable_vccpint_alaram=false ot_alaram=false user_temp_alaram=true timing_mode=continuous
channel_averaging=None sequencer_mode=on startup_channel_selection=contineous_sequence
xlconcat/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED in0_width=1 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in20_width=1 in21_width=1 in22_width=1
in23_width=1 in24_width=1 in25_width=1 in26_width=1
in27_width=1 in28_width=1 in29_width=1 in30_width=1
in31_width=1 dout_width=15 num_ports=15
xlconcat/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED in0_width=1 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in20_width=1 in21_width=1 in22_width=1
in23_width=1 in24_width=1 in25_width=1 in26_width=1
in27_width=1 in28_width=1 in29_width=1 in30_width=1
in31_width=1 dout_width=3 num_ports=3
xlconcat/3
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlconcat x_ipversion=2.1 x_ipcorerevision=1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED in0_width=8 in1_width=1 in2_width=1
in3_width=1 in4_width=1 in5_width=1 in6_width=1
in7_width=1 in8_width=1 in9_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in20_width=1 in21_width=1 in22_width=1
in23_width=1 in24_width=1 in25_width=1 in26_width=1
in27_width=1 in28_width=1 in29_width=1 in30_width=1
in31_width=1 dout_width=13 num_ports=6
xlslice/1
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlslice x_ipversion=1.0 x_ipcorerevision=-1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED din_width=2 din_from=1 din_to=1
xlslice/2
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlslice x_ipversion=1.0 x_ipcorerevision=-1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED din_width=2 din_from=0 din_to=0
xlslice/3
iptotal=1 x_ipproduct=Vivado 2015.2 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=xlslice x_ipversion=1.0 x_ipcorerevision=-1 x_iplanguage=VHDL
x_ipsimlanguage=MIXED din_width=32 din_from=8 din_to=8

report_utilization
slice_logic
slice_luts_used=38290 slice_luts_fixed=0 slice_luts_available=133800 slice_luts_util_percentage=28.62
lut_as_logic_used=35151 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=26.27
lut_as_memory_used=3139 lut_as_memory_fixed=0 lut_as_memory_available=46200 lut_as_memory_util_percentage=6.79
lut_as_distributed_ram_used=2694 lut_as_distributed_ram_fixed=0 lut_as_shift_register_used=445 lut_as_shift_register_fixed=0
slice_registers_used=35088 slice_registers_fixed=6 slice_registers_available=267600 slice_registers_util_percentage=13.11
register_as_flip_flop_used=35072 register_as_flip_flop_fixed=6 register_as_flip_flop_available=267600 register_as_flip_flop_util_percentage=13.11
register_as_latch_used=0 register_as_latch_fixed=0 register_as_latch_available=267600 register_as_latch_util_percentage=0.00
register_as_and_or_used=16 register_as_and_or_fixed=0 register_as_and_or_available=267600 register_as_and_or_util_percentage=<0.01
f7_muxes_used=877 f7_muxes_fixed=0 f7_muxes_available=66900 f7_muxes_util_percentage=1.31
f8_muxes_used=178 f8_muxes_fixed=0 f8_muxes_available=33450 f8_muxes_util_percentage=0.53
slice_used=13578 slice_fixed=0 slice_available=33450 slice_util_percentage=40.59
slicel_used=8590 slicel_fixed=0 slicem_used=4988 slicem_fixed=0
lut_as_logic_used=35151 lut_as_logic_fixed=0 lut_as_logic_available=133800 lut_as_logic_util_percentage=26.27
using_o5_output_only_used=19 using_o5_output_only_fixed= using_o6_output_only_used=34032 using_o6_output_only_fixed=
using_o5_and_o6_used=1100 using_o5_and_o6_fixed= lut_as_memory_used=3139 lut_as_memory_fixed=0
lut_as_memory_available=46200 lut_as_memory_util_percentage=6.79 lut_as_distributed_ram_used=2694 lut_as_distributed_ram_fixed=0
using_o5_output_only_used=0 using_o5_output_only_fixed= using_o6_output_only_used=1808 using_o6_output_only_fixed=
using_o5_and_o6_used=886 using_o5_and_o6_fixed= lut_as_shift_register_used=445 lut_as_shift_register_fixed=0
using_o5_output_only_used=14 using_o5_output_only_fixed= using_o6_output_only_used=298 using_o6_output_only_fixed=
using_o5_and_o6_used=133 using_o5_and_o6_fixed= lut_flip_flop_pairs_used=45273 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_available=133800 lut_flip_flop_pairs_util_percentage=33.84 fully_used_lut_ff_pairs_used=22678 fully_used_lut_ff_pairs_fixed=
lut_ff_pairs_with_unused_lut_used=7016 lut_ff_pairs_with_unused_lut_fixed= lut_ff_pairs_with_unused_flip_flop_used=15579 lut_ff_pairs_with_unused_flip_flop_fixed=
unique_control_sets_used=1867 minimum_number_of_registers_lost_to_control_set_restriction_used=5360(Lost)
memory
block_ram_tile_used=62.5 block_ram_tile_fixed=0 block_ram_tile_available=365 block_ram_tile_util_percentage=17.12
ramb36_fifo_used=60 ramb36_fifo_fixed=0 ramb36_fifo_available=365 ramb36_fifo_util_percentage=16.44
ramb36e1_only_used=60 ramb18_used=5 ramb18_fixed=0 ramb18_available=730
ramb18_util_percentage=0.68 ramb18e1_only_used=5
dsp
dsps_used=11 dsps_fixed=0 dsps_available=740 dsps_util_percentage=1.49
dsp48e1_only_used=11
clocking
bufgctrl_used=15 bufgctrl_fixed=3 bufgctrl_available=32 bufgctrl_util_percentage=46.88
bufio_used=2 bufio_fixed=1 bufio_available=40 bufio_util_percentage=5.00
bufio_only_used=2 bufio_only_fixed=1 mmcme2_adv_used=4 mmcme2_adv_fixed=3
mmcme2_adv_available=10 mmcme2_adv_util_percentage=40.00 plle2_adv_used=3 plle2_adv_fixed=1
plle2_adv_available=10 plle2_adv_util_percentage=30.00 bufmrce_used=0 bufmrce_fixed=0
bufmrce_available=20 bufmrce_util_percentage=0.00 bufhce_used=1 bufhce_fixed=0
bufhce_available=120 bufhce_util_percentage=0.83 bufr_used=2 bufr_fixed=0
bufr_available=40 bufr_util_percentage=5.00
specific_feature
bscane2_used=1 bscane2_fixed=0 bscane2_available=4 bscane2_util_percentage=25.00
capturee2_used=0 capturee2_fixed=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_fixed=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_fixed=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_fixed=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_fixed=0 icape2_available=2 icape2_util_percentage=0.00
pcie_2_1_used=0 pcie_2_1_fixed=0 pcie_2_1_available=1 pcie_2_1_util_percentage=0.00
startupe2_used=1 startupe2_fixed=0 startupe2_available=1 startupe2_util_percentage=100.00
xadc_used=1 xadc_fixed=0 xadc_available=1 xadc_util_percentage=100.00
primitives
fdre_used=30604 fdre_functional_category=Flop & Latch lut6_used=12061 lut6_functional_category=LUT
lut5_used=6970 lut5_functional_category=LUT lut3_used=5702 lut3_functional_category=LUT
lut4_used=5581 lut4_functional_category=LUT lut2_used=4888 lut2_functional_category=LUT
fdce_used=2618 fdce_functional_category=Flop & Latch ramd64e_used=1808 ramd64e_functional_category=Distributed Memory
ramd32_used=1374 ramd32_functional_category=Distributed Memory carry4_used=1313 carry4_functional_category=CarryLogic
fdse_used=1198 fdse_functional_category=Flop & Latch lut1_used=1049 lut1_functional_category=LUT
muxf7_used=877 muxf7_functional_category=MuxFx fdpe_used=657 fdpe_functional_category=Flop & Latch
rams32_used=398 rams32_functional_category=Distributed Memory srl16e_used=364 srl16e_functional_category=Distributed Memory
srlc32e_used=200 srlc32e_functional_category=Distributed Memory muxf8_used=178 muxf8_functional_category=MuxFx
ibuf_used=89 ibuf_functional_category=IO obuft_used=71 obuft_functional_category=IO
obuf_used=63 obuf_functional_category=IO ramb36e1_used=60 ramb36e1_functional_category=Block Memory
oserdese2_used=51 oserdese2_functional_category=IO idelaye2_used=24 idelaye2_functional_category=IO
iserdese2_used=22 iserdese2_functional_category=IO oddr_used=20 oddr_functional_category=IO
ibuf_intermdisable_used=16 ibuf_intermdisable_functional_category=IO srlc16e_used=14 srlc16e_functional_category=Distributed Memory
and2b1l_used=14 and2b1l_functional_category=Others dsp48e1_used=11 dsp48e1_functional_category=Block Arithmetic
bufg_used=11 bufg_functional_category=Clock iddr_used=7 iddr_functional_category=IO
obufds_used=6 obufds_functional_category=IO ramb18e1_used=5 ramb18e1_functional_category=Block Memory
obuftds_used=5 obuftds_functional_category=IO ibufds_used=5 ibufds_functional_category=IO
phaser_out_phy_used=4 phaser_out_phy_functional_category=IO out_fifo_used=4 out_fifo_functional_category=IO
mmcme2_adv_used=4 mmcme2_adv_functional_category=Clock ibufds_intermdisable_int_used=4 ibufds_intermdisable_int_functional_category=IO
bufgctrl_used=4 bufgctrl_functional_category=Clock plle2_adv_used=3 plle2_adv_functional_category=Clock
inv_used=3 inv_functional_category=LUT idelayctrl_used=3 idelayctrl_functional_category=IO
phaser_in_phy_used=2 phaser_in_phy_functional_category=IO or2l_used=2 or2l_functional_category=Others
in_fifo_used=2 in_fifo_functional_category=IO gtpe2_channel_used=2 gtpe2_channel_functional_category=IO
bufr_used=2 bufr_functional_category=Clock bufio_used=2 bufio_functional_category=Clock
xadc_used=1 xadc_functional_category=Others startupe2_used=1 startupe2_functional_category=Others
phy_control_used=1 phy_control_functional_category=IO phaser_ref_used=1 phaser_ref_functional_category=IO
ibufds_gte2_used=1 ibufds_gte2_functional_category=IO gtpe2_common_used=1 gtpe2_common_functional_category=IO
bufh_used=1 bufh_functional_category=Clock bscane2_used=1 bscane2_functional_category=Others
io_standard
rsds_25=0 diff_hstl_ii=0 hstl_i=0 diff_sstl18_ii=0
lvcmos15=1 diff_sstl135_r=0 lvttl=0 lvds_25=1
diff_hstl_i=0 hstl_ii=0 hsul_12=0 ppds_25=0
diff_sstl18_i=0 lvcmos12=1 diff_sstl135=0 lvcmos33=1
diff_sstl15_r=0 lvcmos25=1 diff_sstl15=1 lvcmos18=1
diff_hsul_12=0 hstl_i_18=0 hstl_ii_18=0 sstl18_i=0
sstl18_ii=0 sstl15=1 sstl15_r=0 sstl135=0
sstl135_r=0 tmds_33=1 diff_hstl_i_18=0 mini_lvds_25=0
diff_hstl_ii_18=1 pci33_3=0 mobile_ddr=0 diff_mobile_ddr=0
blvds_25=0

router
usage
lut=38888 ff=35093 bram36=60 bram18=5
ctrls=1867 dsp=11 iob=190 bufg=0
global_clocks=15 pll=3 bufr=2 nets=94886
movable_instances=81536 pins=485442 bogomips=0 high_fanout_nets=42
effort=2 threads=2 router_timing_driven=1 timing_constraints_exist=1
congestion_level=0 estimated_expansions=51649842 actual_expansions=45229714 router_runtime=208.591000

synthesis
command_line_options
-part=xc7a200tsbg484-1 -name=default::[not_specified] -top=system_wrapper -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-link_dcps=default::[not_specified] -rtl_load_constraints=default::[not_specified] -bufg=default::12 -fanout_limit=400
-shreg_min_size=5 -mode=default::default -fsm_extraction=one_hot -keep_equivalent_registers=[specified]
-resource_sharing=off -cascade_dsp=default::auto -control_set_opt_threshold=default::auto
usage
elapsed=00:30:19s memory_peak=2092.246MB memory_gain=1708.789MB hls_ip=0