Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:14.7 (WebPack) - P.20131013 Target Family: Virtex5
OS Platform: NT64 Target Device: xc5vlx50t
Project ID (random number) d6e4e8d7e5fb4633b54fa8bd73b97198.3075C007568C48C7A66708C0547EE5C7.2 Target Package: ff1136
Registration ID 210658864_0_0_155 Target Speed: -1
Date Generated 2015-05-26T18:33:23 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-4710MQ CPU @ 2.50GHz CPU Speed 2494 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Accumulators=1
  • 2-bit up accumulator=1
 Adders/Subtractors=24
  • 3-bit adder=3
  • 3-bit subtractor=1
  • 4-bit adder=1
  • 5-bit adder=2
  • 5-bit subtractor=2
  • 6-bit adder=4
  • 6-bit adder carry out=4
  • 6-bit subtractor=3
  • 7-bit adder=2
  • 7-bit addsub=1
  • 8-bit subtractor=1
 Comparators=46
  • 13-bit comparator not equal=4
  • 15-bit comparator equal=1
  • 2-bit comparator equal=5
  • 2-bit comparator greatequal=1
  • 2-bit comparator less=2
  • 3-bit comparator greatequal=2
  • 3-bit comparator lessequal=1
  • 4-bit comparator greatequal=1
  • 4-bit comparator lessequal=2
  • 5-bit comparator equal=1
  • 5-bit comparator greatequal=1
  • 5-bit comparator less=1
  • 5-bit comparator lessequal=5
  • 6-bit comparator less=1
  • 8-bit comparator equal=1
  • 8-bit comparator lessequal=1
  • 8-bit comparator not equal=16
 Counters=106
  • 12-bit up counter=1
  • 2-bit down counter=1
  • 2-bit up counter=2
  • 3-bit down counter=3
  • 3-bit up counter=1
  • 4-bit down counter=2
  • 4-bit up counter=5
  • 5-bit down counter=4
  • 6-bit up counter=2
  • 6-bit updown counter=82
  • 7-bit up counter=1
  • 8-bit down counter=2
 FSMs=9 Multiplexers=15
  • 1-bit 40-to-1 multiplexer=5
  • 1-bit 64-to-1 multiplexer=2
  • 1-bit 8-to-1 multiplexer=8
 Multipliers=2
  • 3x3-bit registered multiplier=2
 Registers=3415
  • Flip-Flops=3415
 Xors=13
  • 1-bit xor2=13
 		MiscellaneousStatistics
  • AGG_BONDED_IO=118
  • AGG_IO=118
  • AGG_LOCED_IO=118
  • AGG_SLICE=1216
  • NUM_BONDED_IOB=118
  • NUM_BSFULL=1121
  • NUM_BSLUTONLY=417
  • NUM_BSREGONLY=1681
  • NUM_BSUSED=3219
  • NUM_BUFG=4
  • NUM_BUFIO=8
  • NUM_DCM_ADV=1
  • NUM_FIFO36_72_EXP=2
  • NUM_FIFO36_EXP=1
  • NUM_IDELAYCTRL=3
  • NUM_ILOGIC=72
  • NUM_IOB_FF=265
  • NUM_IODELAY=80
  • NUM_LOCED_ILOGIC=8
  • NUM_LOCED_IOB=118
  • NUM_LOCED_IODELAY=8
  • NUM_LOCED_SLICEM=8
  • NUM_LOGIC_O5ANDO6=311
  • NUM_LOGIC_O5ONLY=12
  • NUM_LOGIC_O6ONLY=1150
  • NUM_LUT_RT_EXO6=6
  • NUM_LUT_RT_O5=3
  • NUM_LUT_RT_O6=11
  • NUM_OLOGIC=113
  • NUM_PLL_ADV=1
  • NUM_RAMB36_EXP=1
  • NUM_SLICEL=1170
  • NUM_SLICEM=46
  • NUM_SLICE_CARRY4=21
  • NUM_SLICE_CONTROLSET=153
  • NUM_SLICE_CYINIT=1872
  • NUM_SLICE_F7MUX=38
  • NUM_SLICE_FF=2802
  • NUM_SLICE_UNUSEDCTRL=151
  • NUM_SRL_O6ONLY=59
  • NUM_UNUSABLE_FF_BELS=271
 		NetStatistics
  • NumNets_Active=4361
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=439
  • NumNodesOfType_Active_BOUNCEIN=2280
  • NumNodesOfType_Active_BUFGOUT=4
  • NumNodesOfType_Active_CLKPIN=1428
  • NumNodesOfType_Active_CNTRLPIN=510
  • NumNodesOfType_Active_DOUBLE=10710
  • NumNodesOfType_Active_GENERIC=25
  • NumNodesOfType_Active_GLOBAL=274
  • NumNodesOfType_Active_HLONG=72
  • NumNodesOfType_Active_INPUT=8834
  • NumNodesOfType_Active_IOBIN2OUT=153
  • NumNodesOfType_Active_IOBINPUT=640
  • NumNodesOfType_Active_IOBOUTPUT=429
  • NumNodesOfType_Active_OUTBOUND=4296
  • NumNodesOfType_Active_OUTPUT=3899
  • NumNodesOfType_Active_PADINPUT=205
  • NumNodesOfType_Active_PADOUTPUT=82
  • NumNodesOfType_Active_PENT=4300
  • NumNodesOfType_Active_PINBOUNCE=4826
  • NumNodesOfType_Active_PINFEED=11137
  • NumNodesOfType_Active_VLONG=539
  • NumNodesOfType_Gnd_BOUNCEACROSS=7
  • NumNodesOfType_Gnd_BOUNCEIN=99
  • NumNodesOfType_Gnd_CLKPIN=3
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_DOUBLE=5
  • NumNodesOfType_Gnd_HGNDOUT=64
  • NumNodesOfType_Gnd_INPUT=321
  • NumNodesOfType_Gnd_IOBINPUT=20
  • NumNodesOfType_Gnd_OUTBOUND=6
  • NumNodesOfType_Gnd_OUTPUT=6
  • NumNodesOfType_Gnd_PINBOUNCE=123
  • NumNodesOfType_Gnd_PINFEED=348
  • NumNodesOfType_Vcc_BOUNCEIN=2
  • NumNodesOfType_Vcc_CLKPIN=2
  • NumNodesOfType_Vcc_CNTRLPIN=189
  • NumNodesOfType_Vcc_HVCCOUT=2
  • NumNodesOfType_Vcc_INPUT=521
  • NumNodesOfType_Vcc_IOBINPUT=4
  • NumNodesOfType_Vcc_KVCCOUT=280
  • NumNodesOfType_Vcc_PINBOUNCE=90
  • NumNodesOfType_Vcc_PINFEED=716
 SiteStatistics
  • BUFG-BUFGCTRL=4
  • FIFO36_72_EXP-RAMBFIFO36=2
  • FIFO36_EXP-RAMBFIFO36=1
  • IOB-IOBM=63
  • IOB-IOBS=55
  • RAMB36_EXP-RAMBFIFO36=1
  • SLICEL-SLICEM=335
 		SiteSummary
  • BUFG=4
  • BUFG_BUFG=4
  • BUFIO=8
  • BUFIO_BUFIO=8
  • DCM_ADV=1
  • DCM_ADV_DCM_ADV=1
  • FIFO36_72_EXP=2
  • FIFO36_72_EXP_FIFO36_72_EXP=2
  • FIFO36_EXP=1
  • FIFO36_EXP_FIFO36_EXP=1
  • IDELAYCTRL=3
  • IDELAYCTRL_IDELAYCTRL=3
  • ILOGIC=72
  • ILOGIC_IFF=72
  • IOB=118
  • IOB_INBUF=73
  • IOB_OUTBUF=116
  • IOB_PAD=118
  • IOB_PADOUTUSED=9
  • IODELAY=80
  • IODELAY_IODELAY=80
  • OLOGIC=113
  • OLOGIC_OUTFF=113
  • OLOGIC_TFF=80
  • PLL_ADV=1
  • PLL_ADV_PLL_ADV=1
  • RAMB36_EXP=1
  • RAMB36_EXP_RAMB36_EXP=1
  • SLICEL=1170
  • SLICEL_A5LUT=94
  • SLICEL_A6LUT=483
  • SLICEL_AFF=848
  • SLICEL_B5LUT=110
  • SLICEL_B6LUT=381
  • SLICEL_BFF=685
  • SLICEL_C5LUT=65
  • SLICEL_C6LUT=304
  • SLICEL_CARRY4=21
  • SLICEL_CFF=619
  • SLICEL_CYINITGND=6
  • SLICEL_CYINITVCC=3
  • SLICEL_D5LUT=56
  • SLICEL_D6LUT=303
  • SLICEL_DFF=583
  • SLICEL_F7AMUX=16
  • SLICEL_F7BMUX=21
  • SLICEM=46
  • SLICEM_A5LUT=1
  • SLICEM_A6LUT=33
  • SLICEM_AFF=31
  • SLICEM_B6LUT=13
  • SLICEM_BFF=12
  • SLICEM_C6LUT=11
  • SLICEM_CFF=9
  • SLICEM_D6LUT=9
  • SLICEM_DFF=15
  • SLICEM_F7BMUX=1
 
Configuration Data
DCM_ADV
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
 DCM_ADV_DCM_ADV
  • CLKDV_DIVIDE=[2.0:1]
  • CLKFX_DIVIDE=[4:1]
  • CLKFX_MULTIPLY=[3:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DCM_CLKDV_CLKFX_ALIGNMENT=[TRUE:1]
  • DCM_CLKFB_IODLY_MUXINSEL=[PASS:1]
  • DCM_CLKFB_IODLY_MUXOUT_SEL=[PASS:1]
  • DCM_CLKIN_IODLY_MUXINSEL=[PASS:1]
  • DCM_CLKIN_IODLY_MUXOUT_SEL=[PASS:1]
  • DCM_CLKLOST_EN=[DISABLE:1]
  • DCM_COM_PWC_FB_EN=[FALSE:1]
  • DCM_COM_PWC_REF_EN=[FALSE:1]
  • DCM_EXT_FB_EN=[FALSE:1]
  • DCM_INPUTMUX_EN=[FALSE:1]
  • DCM_LOCK_HIGH_B=[FALSE:1]
  • DCM_OPTINV_PSEN=[FALSE:1]
  • DCM_OPTINV_PSINCDEC=[FALSE:1]
  • DCM_OPTINV_RST=[FALSE:1]
  • DCM_OPTINV_SKEW_IN=[FALSE:1]
  • DCM_OPTINV_SKEW_RST=[FALSE:1]
  • DCM_PERFORMANCE_MODE=[MAX_SPEED:1]
  • DCM_PLL_RST_DCM=[FALSE:1]
  • DCM_POWERDOWN_COMMON_EN_B=[TRUE:1]
  • DCM_REG_PWRD_CFG=[FALSE:1]
  • DCM_SCANMODE=[FALSE:1]
  • DCM_UNUSED_TAPS_POWERDOWN=[TRUE:1]
  • DCM_USE_REG_READY=[TRUE:1]
  • DCM_VREF_SOURCE=[VBG_DLL:1]
  • DCM_VREG_ENABLE=[TRUE:1]
  • DCM_WAIT_PLL=[TRUE:1]
  • DESKEW_ADJUST=[16:1]
  • DFS_AVE_FREQ_GAIN=[2.0:1]
  • DFS_AVE_FREQ_SAMPLE_INTERVAL=[2:1]
  • DFS_CFG_BYPASS=[FALSE:1]
  • DFS_EARLY_LOCK=[FALSE:1]
  • DFS_EN=[FALSE:1]
  • DFS_EN_RELRST_B=[FALSE:1]
  • DFS_FAST_UPDATE=[FALSE:1]
  • DFS_FREQUENCY_MODE=[HIGH:1]
  • DFS_MPW_HIGH=[TRUE:1]
  • DFS_MPW_LOW=[TRUE:1]
  • DFS_OSCILLATOR_MODE=[PHASE_FREQ_LOCK:1]
  • DFS_OSC_ON_FX=[FALSE:1]
  • DFS_OUTPUT_PSDLY_ON_CONCUR=[FALSE:1]
  • DFS_PWRD_CLKIN_STOP_B=[TRUE:1]
  • DFS_PWRD_CLKIN_STOP_STICKY_B=[TRUE:1]
  • DFS_PWRD_REPLY_TIMES_OUT_B=[TRUE:1]
  • DFS_REF_ON_FX=[FALSE:1]
  • DFS_SYNC_TO_DLL=[FALSE:1]
  • DLL_CLKFB_STOPPED_PWRD_EN_B=[TRUE:1]
  • DLL_CLKIN_STOPPED_PWRD_EN_B=[TRUE:1]
  • DLL_DESKEW_LOCK_BY1=[FALSE:1]
  • DLL_ETPP_HOLD=[FALSE:1]
  • DLL_FDBKLOST_EN=[FALSE:1]
  • DLL_FREQUENCY_MODE=[HIGH:1]
  • DLL_PERIOD_LOCK_BY1=[FALSE:1]
  • DLL_PHASE_SHIFT_CALIBRATION=[AUTO_DPS:1]
  • DLL_PHASE_SHIFT_LOCK_BY1=[FALSE:1]
  • DLL_PWRD_ON_SCANMODE_B=[TRUE:1]
  • DLL_PWRD_STICKY_B=[TRUE:1]
  • DLL_SYNTH_CLOCK_SPEED=[HALF:1]
  • DLL_ZD1_EN=[FALSE:1]
  • DLL_ZD1_JF_OVERFLOW_HOLD=[FALSE:1]
  • DLL_ZD1_PWC_EN=[FALSE:1]
  • DLL_ZD2_EN=[FALSE:1]
  • DLL_ZD2_JF_OVERFLOW_HOLD=[FALSE:1]
  • DLL_ZD2_PWC_EN=[FALSE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • MUX_INV_PLL_CLK=[FALSE:1]
  • MUX_INV_TEST_CLK=[FALSE:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC:1] [PSINCDEC_INV:0]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
 FIFO36_72_EXP
  • RDCLKL=[RDCLKL:2] [RDCLKL_INV:0]
  • RDCLKU=[RDCLKU:2] [RDCLKU_INV:0]
  • RDEN=[RDEN:2] [RDEN_INV:0]
  • RDRCLKL=[RDRCLKL_INV:0] [RDRCLKL:2]
  • RDRCLKU=[RDRCLKU_INV:0] [RDRCLKU:2]
  • RST=[RST:2] [RST_INV:0]
  • WRCLKL=[WRCLKL_INV:0] [WRCLKL:2]
  • WRCLKU=[WRCLKU_INV:0] [WRCLKU:2]
  • WREN=[WREN:2] [WREN_INV:0]
 FIFO36_72_EXP_FIFO36_72_EXP
  • DO_REG=[1:2]
  • EN_ECC_READ=[FALSE:2]
  • EN_ECC_WRITE=[FALSE:2]
  • EN_SYN=[FALSE:2]
  • FIRST_WORD_FALL_THROUGH=[FALSE:2]
  • RDCLKL=[RDCLKL:2] [RDCLKL_INV:0]
  • RDCLKU=[RDCLKU:2] [RDCLKU_INV:0]
  • RDEN=[RDEN:2] [RDEN_INV:0]
  • RDRCLKL=[RDRCLKL_INV:0] [RDRCLKL:2]
  • RDRCLKU=[RDRCLKU_INV:0] [RDRCLKU:2]
  • RST=[RST:2] [RST_INV:0]
  • WRCLKL=[WRCLKL_INV:0] [WRCLKL:2]
  • WRCLKU=[WRCLKU_INV:0] [WRCLKU:2]
  • WREN=[WREN:2] [WREN_INV:0]
 FIFO36_EXP
  • RDCLKL=[RDCLKL:1] [RDCLKL_INV:0]
  • RDCLKU=[RDCLKU:1] [RDCLKU_INV:0]
  • RDEN=[RDEN:1] [RDEN_INV:0]
  • RDRCLKL=[RDRCLKL_INV:0] [RDRCLKL:1]
  • RDRCLKU=[RDRCLKU_INV:0] [RDRCLKU:1]
  • RST=[RST:1] [RST_INV:0]
  • WRCLKL=[WRCLKL_INV:0] [WRCLKL:1]
  • WRCLKU=[WRCLKU_INV:0] [WRCLKU:1]
  • WREN=[WREN:1] [WREN_INV:0]
 FIFO36_EXP_FIFO36_EXP
  • DATA_WIDTH=[36:1]
  • DO_REG=[1:1]
  • EN_SYN=[TRUE:1]
  • FIRST_WORD_FALL_THROUGH=[FALSE:1]
  • RDCLKL=[RDCLKL:1] [RDCLKL_INV:0]
  • RDCLKU=[RDCLKU:1] [RDCLKU_INV:0]
  • RDEN=[RDEN:1] [RDEN_INV:0]
  • RDRCLKL=[RDRCLKL_INV:0] [RDRCLKL:1]
  • RDRCLKU=[RDRCLKU_INV:0] [RDRCLKU:1]
  • RST=[RST:1] [RST_INV:0]
  • WRCLKL=[WRCLKL_INV:0] [WRCLKL:1]
  • WRCLKU=[WRCLKU_INV:0] [WRCLKU:1]
  • WREN=[WREN:1] [WREN_INV:0]
 IDELAYCTRL_IDELAYCTRL
  • BIAS_MODE=[0:3]
 ILOGIC
  • CLK=[CLK:0] [CLK_INV:72]
  • CLKB=[CLKB_INV:0] [CLKB:64]
 ILOGIC_IFF
  • CK=[CK:0] [CK_INV:72]
  • CKB=[CKB_INV:0] [CKB:64]
  • DDR_CLK_EDGE=[SAME_EDGE:64]
  • IFFTYPE=[FF:8] [DDR:64]
  • INIT_Q1=[0:72]
  • INIT_Q2=[0:64]
  • SRTYPE=[ASYNC:8]
  • SRVAL_Q1=[1:8]
 IOB_INBUF
  • DIFF_TERM=[FALSE:1]
 IODELAY
  • C=[C:80] [C_INV:0]
  • DATAIN=[DATAIN_INV:0] [DATAIN:8]
 IODELAY_IODELAY
  • C=[C:80] [C_INV:0]
  • DATAIN=[DATAIN_INV:0] [DATAIN:8]
  • DELAYCHAIN_OSC=[FALSE:80]
  • DELAY_SRC=[I:72] [DATAIN:8]
  • HIGH_PERFORMANCE_MODE=[TRUE:80]
  • IDELAY_TYPE=[VARIABLE:80]
  • IDELAY_VALUE=[0:80]
  • ODELAY_VALUE=[0:80]
  • SELFBIASED=[FALSE:80]
  • SIGNAL_PATTERN=[DATA:80]
 OLOGIC
  • CLK=[CLK:97] [CLK_INV:16]
  • D1=[D1:103] [D1_INV:10]
  • D2=[D2:82] [D2_INV:10]
  • T1=[T1_INV:0] [T1:80]
  • T2=[T2:64] [T2_INV:0]
 OLOGIC_OUTFF
  • CK=[CK:97] [CK_INV:16]
  • D1=[D1:103] [D1_INV:10]
  • D2=[D2:82] [D2_INV:10]
  • INIT_OQ=[0:103] [1:10]
  • ODDR_CLK_EDGE=[OPPOSITE_EDGE:20] [SAME_EDGE:72]
  • OUTFFTYPE=[FF:21] [DDR:92]
  • SRTYPE_OQ=[ASYNC:6]
  • SRVAL_OQ=[0:3] [1:3]
 OLOGIC_TFF
  • CK=[CK:64] [CK_INV:16]
  • D1=[D1:80] [D1_INV:0]
  • D2=[D2:64] [D2_INV:0]
  • INIT_TQ=[0:64] [1:16]
  • SRTYPE_TQ=[ASYNC:80]
  • SRVAL_TQ=[1:80]
  • TDDR_CLK_EDGE=[SAME_EDGE:64]
  • TFFTYPE=[FF:16] [DDR:64]
 PLL_ADV
  • CLKINSEL=[CLKINSEL:1] [CLKINSEL_INV:0]
  • REL=[REL_INV:0] [REL:1]
  • RST=[RST:1] [RST_INV:0]
 PLL_ADV_PLL_ADV
  • BANDWIDTH=[OPTIMIZED:1]
  • CLKFBOUT_DESKEW_ADJUST=[0:1]
  • CLKINSEL=[CLKINSEL:1] [CLKINSEL_INV:0]
  • CLKOUT0_DESKEW_ADJUST=[0:1]
  • CLKOUT1_DESKEW_ADJUST=[0:1]
  • CLKOUT2_DESKEW_ADJUST=[0:1]
  • CLKOUT3_DESKEW_ADJUST=[0:1]
  • CLKOUT4_DESKEW_ADJUST=[0:1]
  • CLKOUT5_DESKEW_ADJUST=[0:1]
  • CMT_TEST_CLK_SEL=[7:1]
  • COMPENSATION=[PLL2DCM:1]
  • DIVCLK_DIVIDE=[3:1]
  • EN_REL=[FALSE:1]
  • LOCK_FAST_FILTER=[HIGH:1]
  • LOCK_SLOW_FILTER=[HIGH:1]
  • PLL_2_DCM1_CLK_SEL=[6:1]
  • PLL_2_DCM2_CLK_SEL=[6:1]
  • PLL_AVDD_COMP_SET=[3:1]
  • PLL_AVDD_VBG_PD=[1:1]
  • PLL_AVDD_VBG_SEL=[9:1]
  • PLL_CLK0MX=[0:1]
  • PLL_CLK1MX=[0:1]
  • PLL_CLK2MX=[0:1]
  • PLL_CLK3MX=[0:1]
  • PLL_CLK4MX=[0:1]
  • PLL_CLK5MX=[0:1]
  • PLL_CLKBURST_CNT=[0:1]
  • PLL_CLKBURST_ENABLE=[FALSE:1]
  • PLL_CLKCNTRL=[0:1]
  • PLL_CLKFBMX=[0:1]
  • PLL_CLKFBOUT2_EDGE=[TRUE:1]
  • PLL_CLKFBOUT2_NOCOUNT=[TRUE:1]
  • PLL_CLKFB_MUX_SEL=[0:1]
  • PLL_CLKIN_MUX_SEL=[0:1]
  • PLL_CP_BIAS_TRIP_SHIFT=[FALSE:1]
  • PLL_CP_RES=[1:1]
  • PLL_DIRECT_PATH_CNTRL=[FALSE:1]
  • PLL_DVDD_COMP_SET=[3:1]
  • PLL_DVDD_VBG_PD=[1:1]
  • PLL_DVDD_VBG_SEL=[9:1]
  • PLL_EN=[FALSE:1]
  • PLL_EN_TCLK0=[FALSE:1]
  • PLL_EN_TCLK1=[FALSE:1]
  • PLL_EN_TCLK2=[FALSE:1]
  • PLL_EN_TCLK3=[FALSE:1]
  • PLL_EN_TCLK4=[FALSE:1]
  • PLL_EN_VCO0=[TRUE:1]
  • PLL_EN_VCO1=[TRUE:1]
  • PLL_EN_VCO2=[TRUE:1]
  • PLL_EN_VCO3=[TRUE:1]
  • PLL_EN_VCO4=[TRUE:1]
  • PLL_EN_VCO5=[TRUE:1]
  • PLL_EN_VCO6=[TRUE:1]
  • PLL_EN_VCO7=[TRUE:1]
  • PLL_EN_VCO_DIV1=[FALSE:1]
  • PLL_EN_VCO_DIV6=[FALSE:1]
  • PLL_INC_FLOCK=[TRUE:1]
  • PLL_INC_SLOCK=[TRUE:1]
  • PLL_LF_NEN=[3:1]
  • PLL_LF_PEN=[0:1]
  • PLL_LOCK_CNT=[63:1]
  • PLL_LOCK_CNT_RST_FAST=[FALSE:1]
  • PLL_MAN_LF_EN=[FALSE:1]
  • PLL_NBTI_EN=[FALSE:1]
  • PLL_PFD_CNTRL=[8:1]
  • PLL_PFD_DLY=[1:1]
  • PLL_PMCD_MODE=[FALSE:1]
  • PLL_PWRD_CFG=[FALSE:1]
  • PLL_SEL_SLIPD=[FALSE:1]
  • PLL_SKEW_CNTRL=[0:1]
  • PLL_TCK4_SEL=[0:1]
  • PLL_UNLOCK_CNT=[4:1]
  • PLL_UNLOCK_CNT_RST_FAST=[FALSE:1]
  • PLL_VLFHIGH_DIS=[FALSE:1]
  • REL=[REL_INV:0] [REL:1]
  • RESET_ON_LOSS_OF_LOCK=[FALSE:1]
  • RST=[RST:1] [RST_INV:0]
  • RST_DEASSERT_CLK=[CLKIN1:1]
  • WAIT_DCM1_LOCK=[FALSE:1]
  • WAIT_DCM2_LOCK=[FALSE:1]
 RAMB36_EXP
  • CLKAL=[CLKAL_INV:0] [CLKAL:1]
  • CLKAU=[CLKAU:1] [CLKAU_INV:0]
  • CLKBL=[CLKBL:1] [CLKBL_INV:0]
  • CLKBU=[CLKBU:1] [CLKBU_INV:0]
  • ENAL=[ENAL_INV:0] [ENAL:1]
  • ENAU=[ENAU_INV:0] [ENAU:1]
  • ENBL=[ENBL_INV:0] [ENBL:1]
  • ENBU=[ENBU_INV:0] [ENBU:1]
  • REGCLKAL=[REGCLKAL_INV:0] [REGCLKAL:1]
  • REGCLKAU=[REGCLKAU_INV:0] [REGCLKAU:1]
  • REGCLKBL=[REGCLKBL_INV:1] [REGCLKBL:0]
  • REGCLKBU=[REGCLKBU:0] [REGCLKBU_INV:1]
  • SSRAL=[SSRAL:1] [SSRAL_INV:0]
  • SSRAU=[SSRAU:1] [SSRAU_INV:0]
  • SSRBL=[SSRBL:1] [SSRBL_INV:0]
  • SSRBU=[SSRBU:1] [SSRBU_INV:0]
 RAMB36_EXP_RAMB36_EXP
  • CLKAL=[CLKAL_INV:0] [CLKAL:1]
  • CLKAU=[CLKAU:1] [CLKAU_INV:0]
  • CLKBL=[CLKBL:1] [CLKBL_INV:0]
  • CLKBU=[CLKBU:1] [CLKBU_INV:0]
  • DOA_REG=[1:1]
  • DOB_REG=[0:1]
  • ENAL=[ENAL_INV:0] [ENAL:1]
  • ENAU=[ENAU_INV:0] [ENAU:1]
  • ENBL=[ENBL_INV:0] [ENBL:1]
  • ENBU=[ENBU_INV:0] [ENBU:1]
  • RAM_EXTENSION_A=[NONE:1]
  • RAM_EXTENSION_B=[NONE:1]
  • READ_WIDTH_A=[36:1]
  • READ_WIDTH_B=[36:1]
  • REGCLKAL=[REGCLKAL_INV:0] [REGCLKAL:1]
  • REGCLKAU=[REGCLKAU_INV:0] [REGCLKAU:1]
  • REGCLKBL=[REGCLKBL_INV:1] [REGCLKBL:0]
  • REGCLKBU=[REGCLKBU:0] [REGCLKBU_INV:1]
  • SAVEDATA=[FALSE:1]
  • SSRAL=[SSRAL:1] [SSRAL_INV:0]
  • SSRAU=[SSRAU:1] [SSRAU_INV:0]
  • SSRBL=[SSRBL:1] [SSRBL_INV:0]
  • SSRBU=[SSRBU:1] [SSRBU_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
  • WRITE_WIDTH_A=[0:1]
  • WRITE_WIDTH_B=[0:1]
 SLICEL
  • CLK=[CLK:919] [CLK_INV:100]
 SLICEL_AFF
  • AFFINIT=[INIT0:795] [INIT1:53]
  • AFFSR=[SRLOW:795] [SRHIGH:53]
  • CK=[CK:764] [CK_INV:84]
  • LATCH_OR_FF=[FF:848]
  • SYNC_ATTR=[ASYNC:378] [SYNC:470]
 SLICEL_BFF
  • BFFINIT=[INIT0:641] [INIT1:44]
  • BFFSR=[SRLOW:641] [SRHIGH:44]
  • CK=[CK:622] [CK_INV:63]
  • LATCH_OR_FF=[FF:685]
  • SYNC_ATTR=[ASYNC:323] [SYNC:362]
 SLICEL_CFF
  • CFFINIT=[INIT0:576] [INIT1:43]
  • CFFSR=[SRLOW:576] [SRHIGH:43]
  • CK=[CK:619] [CK_INV:0]
  • LATCH_OR_FF=[FF:619]
  • SYNC_ATTR=[ASYNC:312] [SYNC:307]
 SLICEL_DFF
  • CK=[CK:580] [CK_INV:3]
  • DFFINIT=[INIT0:543] [INIT1:40]
  • DFFSR=[SRLOW:543] [SRHIGH:40]
  • LATCH_OR_FF=[FF:583]
  • SYNC_ATTR=[ASYNC:312] [SYNC:271]
 SLICEM
  • CLK=[CLK:44] [CLK_INV:2]
 SLICEM_A5LUT
  • LUT_OR_MEM=[LUT:1]
 SLICEM_A6LUT
  • A6RAMMODE=[SRL16:23] [SRL32:8]
  • CLK=[CLK:30] [CLK_INV:1]
  • LUT_OR_MEM=[LUT:2] [RAM:31]
 SLICEM_AFF
  • AFFINIT=[INIT0:31]
  • AFFSR=[SRLOW:31]
  • CK=[CK:30] [CK_INV:1]
  • LATCH_OR_FF=[FF:31]
  • SYNC_ATTR=[ASYNC:24] [SYNC:7]
 SLICEM_B6LUT
  • B6RAMMODE=[SRL16:11] [SRL32:1]
  • CLK=[CLK:12] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:1] [RAM:12]
 SLICEM_BFF
  • BFFINIT=[INIT0:12]
  • BFFSR=[SRLOW:12]
  • CK=[CK:12] [CK_INV:0]
  • LATCH_OR_FF=[FF:12]
  • SYNC_ATTR=[ASYNC:11] [SYNC:1]
 SLICEM_C6LUT
  • C6RAMMODE=[SRL16:8] [SRL32:1]
  • CLK=[CLK:9] [CLK_INV:0]
  • LUT_OR_MEM=[LUT:2] [RAM:9]
 SLICEM_CFF
  • CFFINIT=[INIT0:9]
  • CFFSR=[SRLOW:9]
  • CK=[CK:9] [CK_INV:0]
  • LATCH_OR_FF=[FF:9]
  • SYNC_ATTR=[ASYNC:8] [SYNC:1]
 SLICEM_D5LUT
  • LUT_OR_MEM=[LUT:1]
 SLICEM_D6LUT
  • CLK=[CLK:6] [CLK_INV:1]
  • D6RAMMODE=[SRL16:6] [SRL32:1]
  • LUT_OR_MEM=[LUT:2] [RAM:7]
 SLICEM_DFF
  • CK=[CK:14] [CK_INV:1]
  • DFFINIT=[INIT0:15]
  • DFFSR=[SRLOW:15]
  • LATCH_OR_FF=[FF:15]
  • SYNC_ATTR=[ASYNC:6] [SYNC:9]
 
Pin Data
BUFG
  • I0=4
  • O=4
 BUFG_BUFG
  • I0=4
  • O=4
 BUFIO
  • I=8
  • O=8
 BUFIO_BUFIO
  • I=8
  • O=8
 DCM_ADV
  • CLK0=1
  • CLK90=1
  • CLKDV=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DADDR5=1
  • DADDR6=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DO2=1
  • DWE=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 DCM_ADV_DCM_ADV
  • CLK0=1
  • CLK90=1
  • CLKDV=1
  • CLKFB=1
  • CLKFX=1
  • CLKIN=1
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DADDR5=1
  • DADDR6=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DO2=1
  • DWE=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
 FIFO36_72_EXP
  • ALMOSTFULL=1
  • DI0=2
  • DI1=2
  • DI10=2
  • DI11=2
  • DI12=2
  • DI13=2
  • DI14=2
  • DI15=2
  • DI16=2
  • DI17=2
  • DI18=2
  • DI19=2
  • DI2=2
  • DI20=2
  • DI21=2
  • DI22=2
  • DI23=2
  • DI24=2
  • DI25=2
  • DI26=2
  • DI27=2
  • DI28=2
  • DI29=2
  • DI3=2
  • DI30=2
  • DI31=2
  • DI32=2
  • DI33=2
  • DI34=2
  • DI35=2
  • DI36=2
  • DI37=2
  • DI38=2
  • DI39=2
  • DI4=2
  • DI40=2
  • DI41=2
  • DI42=2
  • DI43=2
  • DI44=2
  • DI45=2
  • DI46=2
  • DI47=2
  • DI48=2
  • DI49=2
  • DI5=2
  • DI50=2
  • DI51=2
  • DI52=2
  • DI53=2
  • DI54=2
  • DI55=2
  • DI56=2
  • DI57=2
  • DI58=2
  • DI59=2
  • DI6=2
  • DI60=2
  • DI61=2
  • DI62=2
  • DI63=2
  • DI7=2
  • DI8=2
  • DI9=2
  • DIP0=2
  • DIP1=2
  • DIP2=2
  • DIP3=2
  • DIP4=2
  • DIP5=2
  • DIP6=2
  • DIP7=2
  • DO0=2
  • DO1=2
  • DO10=2
  • DO11=2
  • DO12=2
  • DO13=2
  • DO14=2
  • DO15=2
  • DO16=2
  • DO17=2
  • DO18=2
  • DO19=2
  • DO2=2
  • DO20=2
  • DO21=2
  • DO22=2
  • DO23=2
  • DO24=2
  • DO25=2
  • DO26=2
  • DO27=2
  • DO28=2
  • DO29=2
  • DO3=2
  • DO30=2
  • DO31=2
  • DO32=2
  • DO33=2
  • DO34=2
  • DO35=2
  • DO36=2
  • DO37=2
  • DO38=2
  • DO39=2
  • DO4=2
  • DO40=2
  • DO41=2
  • DO42=2
  • DO43=2
  • DO44=2
  • DO45=2
  • DO46=2
  • DO47=2
  • DO48=2
  • DO49=2
  • DO5=2
  • DO50=2
  • DO51=2
  • DO52=2
  • DO53=2
  • DO54=2
  • DO55=2
  • DO56=2
  • DO57=2
  • DO58=2
  • DO59=2
  • DO6=2
  • DO60=2
  • DO61=2
  • DO62=2
  • DO63=2
  • DO7=2
  • DO8=2
  • DO9=2
  • DOP0=2
  • DOP1=2
  • DOP2=2
  • DOP3=2
  • DOP4=2
  • DOP5=2
  • DOP6=2
  • DOP7=2
  • RDCLKL=2
  • RDCLKU=2
  • RDEN=2
  • RDRCLKL=2
  • RDRCLKU=2
  • RST=2
  • TIEOFFREGCEAL=2
  • TIEOFFREGCEAU=2
  • WRCLKL=2
  • WRCLKU=2
  • WREN=2
 FIFO36_72_EXP_FIFO36_72_EXP
  • ALMOSTFULL=1
  • DI0=2
  • DI1=2
  • DI10=2
  • DI11=2
  • DI12=2
  • DI13=2
  • DI14=2
  • DI15=2
  • DI16=2
  • DI17=2
  • DI18=2
  • DI19=2
  • DI2=2
  • DI20=2
  • DI21=2
  • DI22=2
  • DI23=2
  • DI24=2
  • DI25=2
  • DI26=2
  • DI27=2
  • DI28=2
  • DI29=2
  • DI3=2
  • DI30=2
  • DI31=2
  • DI32=2
  • DI33=2
  • DI34=2
  • DI35=2
  • DI36=2
  • DI37=2
  • DI38=2
  • DI39=2
  • DI4=2
  • DI40=2
  • DI41=2
  • DI42=2
  • DI43=2
  • DI44=2
  • DI45=2
  • DI46=2
  • DI47=2
  • DI48=2
  • DI49=2
  • DI5=2
  • DI50=2
  • DI51=2
  • DI52=2
  • DI53=2
  • DI54=2
  • DI55=2
  • DI56=2
  • DI57=2
  • DI58=2
  • DI59=2
  • DI6=2
  • DI60=2
  • DI61=2
  • DI62=2
  • DI63=2
  • DI7=2
  • DI8=2
  • DI9=2
  • DIP0=2
  • DIP1=2
  • DIP2=2
  • DIP3=2
  • DIP4=2
  • DIP5=2
  • DIP6=2
  • DIP7=2
  • DO0=2
  • DO1=2
  • DO10=2
  • DO11=2
  • DO12=2
  • DO13=2
  • DO14=2
  • DO15=2
  • DO16=2
  • DO17=2
  • DO18=2
  • DO19=2
  • DO2=2
  • DO20=2
  • DO21=2
  • DO22=2
  • DO23=2
  • DO24=2
  • DO25=2
  • DO26=2
  • DO27=2
  • DO28=2
  • DO29=2
  • DO3=2
  • DO30=2
  • DO31=2
  • DO32=2
  • DO33=2
  • DO34=2
  • DO35=2
  • DO36=2
  • DO37=2
  • DO38=2
  • DO39=2
  • DO4=2
  • DO40=2
  • DO41=2
  • DO42=2
  • DO43=2
  • DO44=2
  • DO45=2
  • DO46=2
  • DO47=2
  • DO48=2
  • DO49=2
  • DO5=2
  • DO50=2
  • DO51=2
  • DO52=2
  • DO53=2
  • DO54=2
  • DO55=2
  • DO56=2
  • DO57=2
  • DO58=2
  • DO59=2
  • DO6=2
  • DO60=2
  • DO61=2
  • DO62=2
  • DO63=2
  • DO7=2
  • DO8=2
  • DO9=2
  • DOP0=2
  • DOP1=2
  • DOP2=2
  • DOP3=2
  • DOP4=2
  • DOP5=2
  • DOP6=2
  • DOP7=2
  • RDCLKL=2
  • RDCLKU=2
  • RDEN=2
  • RDRCLKL=2
  • RDRCLKU=2
  • RST=2
  • TIEOFFREGCEAL=2
  • TIEOFFREGCEAU=2
  • WRCLKL=2
  • WRCLKU=2
  • WREN=2
 FIFO36_EXP
  • ALMOSTFULL=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI16=1
  • DI17=1
  • DI18=1
  • DI19=1
  • DI2=1
  • DI20=1
  • DI21=1
  • DI22=1
  • DI23=1
  • DI24=1
  • DI25=1
  • DI26=1
  • DI27=1
  • DI28=1
  • DI29=1
  • DI3=1
  • DI30=1
  • DI31=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DIP0=1
  • DIP1=1
  • DIP2=1
  • DIP3=1
  • DO0=1
  • DO1=1
  • DO10=1
  • DO11=1
  • DO12=1
  • DO13=1
  • DO14=1
  • DO15=1
  • DO16=1
  • DO17=1
  • DO18=1
  • DO19=1
  • DO2=1
  • DO20=1
  • DO21=1
  • DO22=1
  • DO23=1
  • DO24=1
  • DO3=1
  • DO31=1
  • DO4=1
  • DO5=1
  • DO6=1
  • DO7=1
  • DO8=1
  • DO9=1
  • DOP0=1
  • DOP1=1
  • EMPTY=1
  • RDCLKL=1
  • RDCLKU=1
  • RDEN=1
  • RDRCLKL=1
  • RDRCLKU=1
  • RST=1
  • TIEOFFREGCEAL=1
  • TIEOFFREGCEAU=1
  • WRCLKL=1
  • WRCLKU=1
  • WREN=1
 FIFO36_EXP_FIFO36_EXP
  • ALMOSTFULL=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI16=1
  • DI17=1
  • DI18=1
  • DI19=1
  • DI2=1
  • DI20=1
  • DI21=1
  • DI22=1
  • DI23=1
  • DI24=1
  • DI25=1
  • DI26=1
  • DI27=1
  • DI28=1
  • DI29=1
  • DI3=1
  • DI30=1
  • DI31=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DIP0=1
  • DIP1=1
  • DIP2=1
  • DIP3=1
  • DO0=1
  • DO1=1
  • DO10=1
  • DO11=1
  • DO12=1
  • DO13=1
  • DO14=1
  • DO15=1
  • DO16=1
  • DO17=1
  • DO18=1
  • DO19=1
  • DO2=1
  • DO20=1
  • DO21=1
  • DO22=1
  • DO23=1
  • DO24=1
  • DO3=1
  • DO31=1
  • DO4=1
  • DO5=1
  • DO6=1
  • DO7=1
  • DO8=1
  • DO9=1
  • DOP0=1
  • DOP1=1
  • EMPTY=1
  • RDCLKL=1
  • RDCLKU=1
  • RDEN=1
  • RDRCLKL=1
  • RDRCLKU=1
  • RST=1
  • TIEOFFREGCEAL=1
  • TIEOFFREGCEAU=1
  • WRCLKL=1
  • WRCLKU=1
  • WREN=1
 IDELAYCTRL
  • RDY=3
  • REFCLK=3
  • RST=3
 IDELAYCTRL_IDELAYCTRL
  • RDY=3
  • REFCLK=3
  • RST=3
 ILOGIC
  • CE1=64
  • CLK=72
  • CLKB=64
  • DDLY=72
  • Q1=72
  • Q2=64
  • SR=8
 ILOGIC_IFF
  • CE=64
  • CK=72
  • CKB=64
  • D=72
  • Q1=72
  • Q2=64
  • SR=8
 IOB
  • DIFFI_IN=9
  • I=73
  • O=116
  • PAD=118
  • PADOUT=9
  • T=80
 IOB_INBUF
  • DIFFI_IN=9
  • OUT=73
  • PAD=73
 IOB_OUTBUF
  • IN=116
  • OUT=116
  • TRI=80
 IOB_PAD
  • PAD=118
 IOB_PADOUTUSED
  • 0=9
  • OUT=9
 IODELAY
  • C=80
  • CE=80
  • DATAIN=8
  • DATAOUT=80
  • IDATAIN=72
  • INC=80
  • RST=80
 IODELAY_IODELAY
  • C=80
  • CE=80
  • DATAIN=8
  • DATAOUT=80
  • IDATAIN=72
  • INC=80
  • RST=80
 OLOGIC
  • CLK=113
  • D1=113
  • D2=92
  • OCE=95
  • OQ=113
  • REV=3
  • SR=86
  • T1=80
  • T2=64
  • TCE=64
  • TQ=80
 OLOGIC_OUTFF
  • CE=95
  • CK=113
  • D1=113
  • D2=92
  • Q=113
  • REV=3
  • SR=6
 OLOGIC_TFF
  • CE=64
  • CK=80
  • D1=80
  • D2=64
  • Q=80
  • SR=80
 PLL_ADV
  • CLKFBDCM=1
  • CLKFBIN=1
  • CLKIN1=1
  • CLKINSEL=1
  • CLKOUTDCM0=1
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DWE=1
  • LOCKED=1
  • REL=1
  • RST=1
 PLL_ADV_PLL_ADV
  • CLKFBDCM=1
  • CLKFBIN=1
  • CLKIN1=1
  • CLKINSEL=1
  • CLKOUTDCM0=1
  • DADDR0=1
  • DADDR1=1
  • DADDR2=1
  • DADDR3=1
  • DADDR4=1
  • DCLK=1
  • DEN=1
  • DI0=1
  • DI1=1
  • DI10=1
  • DI11=1
  • DI12=1
  • DI13=1
  • DI14=1
  • DI15=1
  • DI2=1
  • DI3=1
  • DI4=1
  • DI5=1
  • DI6=1
  • DI7=1
  • DI8=1
  • DI9=1
  • DWE=1
  • LOCKED=1
  • REL=1
  • RST=1
 RAMB36_EXP
  • ADDRAL10=1
  • ADDRAL11=1
  • ADDRAL12=1
  • ADDRAL13=1
  • ADDRAL14=1
  • ADDRAL15=1
  • ADDRAL5=1
  • ADDRAL6=1
  • ADDRAL7=1
  • ADDRAL8=1
  • ADDRAL9=1
  • ADDRAU10=1
  • ADDRAU11=1
  • ADDRAU12=1
  • ADDRAU13=1
  • ADDRAU14=1
  • ADDRAU5=1
  • ADDRAU6=1
  • ADDRAU7=1
  • ADDRAU8=1
  • ADDRAU9=1
  • ADDRBL10=1
  • ADDRBL11=1
  • ADDRBL12=1
  • ADDRBL13=1
  • ADDRBL14=1
  • ADDRBL15=1
  • ADDRBL5=1
  • ADDRBL6=1
  • ADDRBL7=1
  • ADDRBL8=1
  • ADDRBL9=1
  • ADDRBU10=1
  • ADDRBU11=1
  • ADDRBU12=1
  • ADDRBU13=1
  • ADDRBU14=1
  • ADDRBU5=1
  • ADDRBU6=1
  • ADDRBU7=1
  • ADDRBU8=1
  • ADDRBU9=1
  • CLKAL=1
  • CLKAU=1
  • CLKBL=1
  • CLKBU=1
  • DOA0=1
  • DOA1=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA16=1
  • DOA17=1
  • DOA18=1
  • DOA19=1
  • DOA2=1
  • DOA20=1
  • DOA21=1
  • DOA22=1
  • DOA23=1
  • DOA24=1
  • DOA28=1
  • DOA29=1
  • DOA3=1
  • DOA31=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENAL=1
  • ENAU=1
  • ENBL=1
  • ENBU=1
  • REGCEAL=1
  • REGCEAU=1
  • REGCEBL=1
  • REGCEBU=1
  • REGCLKAL=1
  • REGCLKAU=1
  • REGCLKBL=1
  • REGCLKBU=1
  • SSRAL=1
  • SSRAU=1
  • SSRBL=1
  • SSRBU=1
  • WEAL0=1
  • WEAL1=1
  • WEAL2=1
  • WEAL3=1
  • WEAU0=1
  • WEAU1=1
  • WEAU2=1
  • WEAU3=1
  • WEBL0=1
  • WEBL1=1
  • WEBL2=1
  • WEBL3=1
  • WEBL4=1
  • WEBL5=1
  • WEBL6=1
  • WEBL7=1
  • WEBU0=1
  • WEBU1=1
  • WEBU2=1
  • WEBU3=1
  • WEBU4=1
  • WEBU5=1
  • WEBU6=1
  • WEBU7=1
 RAMB36_EXP_RAMB36_EXP
  • ADDRAL10=1
  • ADDRAL11=1
  • ADDRAL12=1
  • ADDRAL13=1
  • ADDRAL14=1
  • ADDRAL15=1
  • ADDRAL5=1
  • ADDRAL6=1
  • ADDRAL7=1
  • ADDRAL8=1
  • ADDRAL9=1
  • ADDRAU10=1
  • ADDRAU11=1
  • ADDRAU12=1
  • ADDRAU13=1
  • ADDRAU14=1
  • ADDRAU5=1
  • ADDRAU6=1
  • ADDRAU7=1
  • ADDRAU8=1
  • ADDRAU9=1
  • ADDRBL10=1
  • ADDRBL11=1
  • ADDRBL12=1
  • ADDRBL13=1
  • ADDRBL14=1
  • ADDRBL15=1
  • ADDRBL5=1
  • ADDRBL6=1
  • ADDRBL7=1
  • ADDRBL8=1
  • ADDRBL9=1
  • ADDRBU10=1
  • ADDRBU11=1
  • ADDRBU12=1
  • ADDRBU13=1
  • ADDRBU14=1
  • ADDRBU5=1
  • ADDRBU6=1
  • ADDRBU7=1
  • ADDRBU8=1
  • ADDRBU9=1
  • CLKAL=1
  • CLKAU=1
  • CLKBL=1
  • CLKBU=1
  • DOA0=1
  • DOA1=1
  • DOA12=1
  • DOA13=1
  • DOA14=1
  • DOA15=1
  • DOA16=1
  • DOA17=1
  • DOA18=1
  • DOA19=1
  • DOA2=1
  • DOA20=1
  • DOA21=1
  • DOA22=1
  • DOA23=1
  • DOA24=1
  • DOA28=1
  • DOA29=1
  • DOA3=1
  • DOA31=1
  • DOA4=1
  • DOA5=1
  • DOA6=1
  • DOA7=1
  • DOA8=1
  • DOA9=1
  • DOPA0=1
  • DOPA1=1
  • ENAL=1
  • ENAU=1
  • ENBL=1
  • ENBU=1
  • REGCEAL=1
  • REGCEAU=1
  • REGCEBL=1
  • REGCEBU=1
  • REGCLKAL=1
  • REGCLKAU=1
  • REGCLKBL=1
  • REGCLKBU=1
  • SSRAL=1
  • SSRAU=1
  • SSRBL=1
  • SSRBU=1
  • WEAL0=1
  • WEAL1=1
  • WEAL2=1
  • WEAL3=1
  • WEAU0=1
  • WEAU1=1
  • WEAU2=1
  • WEAU3=1
  • WEBL0=1
  • WEBL1=1
  • WEBL2=1
  • WEBL3=1
  • WEBL4=1
  • WEBL5=1
  • WEBL6=1
  • WEBL7=1
  • WEBU0=1
  • WEBU1=1
  • WEBU2=1
  • WEBU3=1
  • WEBU4=1
  • WEBU5=1
  • WEBU6=1
  • WEBU7=1
 SLICEL
  • A=198
  • A1=239
  • A2=330
  • A3=358
  • A4=450
  • A5=444
  • A6=460
  • AMUX=25
  • AQ=848
  • AX=534
  • B=179
  • B1=167
  • B2=250
  • B3=303
  • B4=358
  • B5=367
  • B6=381
  • BMUX=35
  • BQ=685
  • BX=442
  • C=94
  • C1=159
  • C2=221
  • C3=247
  • C4=290
  • C5=293
  • C6=303
  • CE=89
  • CIN=11
  • CLK=1019
  • CMUX=29
  • COUT=11
  • CQ=619
  • CX=410
  • D=128
  • D1=140
  • D2=193
  • D3=223
  • D4=283
  • D5=290
  • D6=299
  • DMUX=17
  • DQ=583
  • DX=437
  • SR=318
 SLICEL_A5LUT
  • A1=57
  • A2=74
  • A3=79
  • A4=76
  • A5=73
  • O5=94
 SLICEL_A6LUT
  • A1=202
  • A2=294
  • A3=355
  • A4=442
  • A5=444
  • A6=460
  • O6=483
 SLICEL_AFF
  • CE=77
  • CK=848
  • D=848
  • Q=848
  • REV=29
  • SR=247
 SLICEL_B5LUT
  • A1=57
  • A2=70
  • A3=103
  • A4=99
  • A5=98
  • O5=110
 SLICEL_B6LUT
  • A1=118
  • A2=205
  • A3=295
  • A4=336
  • A5=367
  • A6=381
  • O6=381
 SLICEL_BFF
  • CE=67
  • CK=685
  • D=685
  • Q=685
  • REV=19
  • SR=162
 SLICEL_C5LUT
  • A1=43
  • A2=50
  • A3=57
  • A4=55
  • A5=56
  • O5=65
 SLICEL_C6LUT
  • A1=126
  • A2=187
  • A3=245
  • A4=289
  • A5=293
  • A6=303
  • O6=304
 SLICEL_CARRY4
  • CIN=11
  • CO0=5
  • CO3=11
  • CYINIT=10
  • DI0=21
  • DI1=15
  • DI2=14
  • DI3=11
  • O0=11
  • O1=11
  • O2=10
  • O3=9
  • S0=21
  • S1=16
  • S2=15
  • S3=14
 SLICEL_CFF
  • CE=66
  • CK=619
  • D=619
  • Q=619
  • REV=14
  • SR=158
 SLICEL_CYINITGND
  • 0=6
 SLICEL_CYINITVCC
  • 1=3
 SLICEL_D5LUT
  • A1=39
  • A2=44
  • A3=49
  • A4=49
  • A5=48
  • O5=56
 SLICEL_D6LUT
  • A1=104
  • A2=156
  • A3=218
  • A4=280
  • A5=289
  • A6=299
  • O6=303
 SLICEL_DFF
  • CE=51
  • CK=583
  • D=583
  • Q=583
  • REV=8
  • SR=125
 SLICEL_F7AMUX
  • 0=16
  • 1=16
  • OUT=16
  • S0=16
 SLICEL_F7BMUX
  • 0=21
  • 1=21
  • OUT=21
  • S0=21
 SLICEM
  • A=2
  • A1=32
  • A2=32
  • A3=32
  • A4=33
  • A5=33
  • A6=33
  • AI=23
  • AMUX=1
  • AQ=31
  • AX=8
  • B=1
  • B1=13
  • B2=13
  • B3=13
  • B4=13
  • B5=13
  • B6=13
  • BI=11
  • BQ=12
  • BX=1
  • C=1
  • C1=10
  • C2=10
  • C3=10
  • C4=10
  • C5=11
  • C6=11
  • CE=38
  • CI=8
  • CLK=46
  • CMUX=1
  • CQ=9
  • CX=2
  • D=1
  • D1=9
  • D2=9
  • D3=9
  • D4=9
  • D5=9
  • D6=9
  • DI=6
  • DQ=15
  • DX=9
 SLICEM_A5LUT
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • O5=1
 SLICEM_A6LUT
  • A1=32
  • A2=32
  • A3=32
  • A4=33
  • A5=33
  • A6=33
  • CLK=31
  • DI1=8
  • DI2=23
  • O6=33
  • WE=31
 SLICEM_AFF
  • CK=31
  • D=31
  • Q=31
 SLICEM_B6LUT
  • A1=13
  • A2=13
  • A3=13
  • A4=13
  • A5=13
  • A6=13
  • CLK=12
  • DI1=1
  • DI2=11
  • O6=13
  • WE=12
 SLICEM_BFF
  • CK=12
  • D=12
  • Q=12
 SLICEM_C6LUT
  • A1=10
  • A2=10
  • A3=10
  • A4=10
  • A5=11
  • A6=11
  • CLK=9
  • DI1=1
  • DI2=8
  • O6=11
  • WE=9
 SLICEM_CFF
  • CK=9
  • D=9
  • Q=9
 SLICEM_D5LUT
  • A1=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • O5=1
 SLICEM_D6LUT
  • A1=9
  • A2=9
  • A3=9
  • A4=9
  • A5=9
  • A6=9
  • CLK=7
  • DI1=1
  • DI2=6
  • O6=9
  • WE=7
 SLICEM_DFF
  • CK=15
  • D=15
  • Q=15
 SLICEM_F7BMUX
  • 0=1
  • 1=1
  • OUT=1
  • S0=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -uc <fname>.ucf -p xc5vlx50t-ff1136-1 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc5vlx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 53 50 0 0 0 0 0
arwz 10 10 0 0 0 0 0
bitgen 67 66 0 0 0 0 0
map 67 67 0 0 0 0 0
ngc2edif 3 3 0 0 0 0 0
ngdbuild 76 76 0 0 0 0 0
par 67 67 0 0 0 0 0
trce 65 65 0 0 0 0 0
xawinfo 1 1 0 0 0 0 0
xst 99 96 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/wizards/arwz/awz_db_dcmgen_virtex4.htm ( 2 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PreTrceFastPath=false
PROP_PropSpecInProjFile=Store all values PROP_ReduceControlSets_virtex5=Auto
PROP_Simulator=Modelsim-SE Mixed PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2015-05-26T16:19:00
PROP_intWbtProjectID=3075C007568C48C7A66708C0547EE5C7 PROP_intWbtProjectIteration=2
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone_virtex5=true PROP_xilxPreTrceRpt=Error Report
PROP_xstLUTCombining_virtex5=Auto PROP_xstLibSearchOrder=changed
PROP_AutoTop=true PROP_DevFamily=Virtex5
PROP_DevDevice=xc5vlx50t PROP_DevFamilyPMName=virtex5
PROP_DevPackage=ff1136 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-1 PROP_PreferredLanguage=Verilog
FILE_UCF=2 FILE_VERILOG=25
FILE_XAW=1
 
Core Statistics
Core Type=mig_v3_61
ADDITIVE_LAT=0 BANK_WIDTH=2 BURST_LEN=4 BURST_TYPE=0
CAS_LAT=4 CKE_WIDTH=1 CLK_PERIOD=3750 CLK_WIDTH=2
COL_WIDTH=10 CS_NUM=1 CS_WIDTH=1 DM_WIDTH=8
DQS_WIDTH=8 DQ_PER_DQS=8 DQ_WIDTH=64 ECC_ENABLE=0
INTERFACE_TYPE=DDR2_SDRAM LANGUAGE=Verilog MULTI_BANK_EN=1 NO_OF_CONTROLLERS=1
ODT_TYPE=3 ODT_WIDTH=1 REDUCE_DRV=0 REG_ENABLE=0
ROW_WIDTH=13 RST_ACT_LOW=1 SYNTHESIS_TOOL=ISE TRAS=40000
TRCD=15000 TREFI_NS=7800 TRFC=105000 TRP=15000
TRTP=7500 TWO_T_TIME_EN=1 TWR=15000 TWTR=7500
Core Type=mig_v3_61
ADDITIVE_LAT=0 BANK_WIDTH=2 BURST_LEN=4 BURST_TYPE=0
CAS_LAT=4 CKE_WIDTH=1 CLK_PERIOD=3750 CLK_WIDTH=2
COL_WIDTH=10 CS_NUM=1 CS_WIDTH=1 DM_WIDTH=8
DQS_WIDTH=8 DQ_PER_DQS=8 DQ_WIDTH=64 ECC_ENABLE=0
INTERFACE_TYPE=DDR2_SDRAM LANGUAGE=Verilog MULTI_BANK_EN=1 NO_OF_CONTROLLERS=1
ODT_TYPE=3 ODT_WIDTH=1 REDUCE_DRV=0 REG_ENABLE=0
ROW_WIDTH=13 RST_ACT_LOW=1 SYNTHESIS_TOOL=ISE TRAS=40000
TRCD=15000 TREFI_NS=7800 TRFC=105000 TRP=15000
TRTP=7500 TWO_T_TIME_EN=1 TWR=15000 TWTR=7500
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_BUFIO=8 NGDBUILD_NUM_DCM_ADV=1 NGDBUILD_NUM_FD=1033
NGDBUILD_NUM_FDCPE=21 NGDBUILD_NUM_FDCPE_1=8 NGDBUILD_NUM_FDE=201 NGDBUILD_NUM_FDP=113
NGDBUILD_NUM_FDPE=34 NGDBUILD_NUM_FDR=354 NGDBUILD_NUM_FDRE=122 NGDBUILD_NUM_FDRS=68
NGDBUILD_NUM_FDRSE=782 NGDBUILD_NUM_FDRSE_1=136 NGDBUILD_NUM_FDR_1=1 NGDBUILD_NUM_FDS=20
NGDBUILD_NUM_FDSE=19 NGDBUILD_NUM_FDS_1=3 NGDBUILD_NUM_FD_1=2 NGDBUILD_NUM_FIFO36_72_EXP=2
NGDBUILD_NUM_FIFO36_EXP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUFGDS=1 NGDBUILD_NUM_IDDR_2CLK=64
NGDBUILD_NUM_IDELAYCTRL=1 NGDBUILD_NUM_INV=69 NGDBUILD_NUM_IOBUF=64 NGDBUILD_NUM_IOBUFDS=8
NGDBUILD_NUM_IODELAY=80 NGDBUILD_NUM_LUT1=12 NGDBUILD_NUM_LUT2=120 NGDBUILD_NUM_LUT3=430
NGDBUILD_NUM_LUT4=161 NGDBUILD_NUM_LUT5=498 NGDBUILD_NUM_LUT6=520 NGDBUILD_NUM_MUXCY=61
NGDBUILD_NUM_MUXF7=40 NGDBUILD_NUM_OBUF=32 NGDBUILD_NUM_OBUFDS=2 NGDBUILD_NUM_ODDR=146
NGDBUILD_NUM_OR2=1 NGDBUILD_NUM_PLL_ADV=1 NGDBUILD_NUM_RAMB36_EXP=1 NGDBUILD_NUM_SRL16=1
NGDBUILD_NUM_SRLC16E=47 NGDBUILD_NUM_SRLC32E=18 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=41
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_BUFIO=8 NGDBUILD_NUM_DCM_ADV=1 NGDBUILD_NUM_FD=1033
NGDBUILD_NUM_FDCPE=21 NGDBUILD_NUM_FDCPE_1=8 NGDBUILD_NUM_FDE=201 NGDBUILD_NUM_FDP=113
NGDBUILD_NUM_FDPE=34 NGDBUILD_NUM_FDR=354 NGDBUILD_NUM_FDRE=122 NGDBUILD_NUM_FDRS=68
NGDBUILD_NUM_FDRSE=782 NGDBUILD_NUM_FDRSE_1=136 NGDBUILD_NUM_FDR_1=1 NGDBUILD_NUM_FDS=20
NGDBUILD_NUM_FDSE=19 NGDBUILD_NUM_FDS_1=3 NGDBUILD_NUM_FD_1=2 NGDBUILD_NUM_FIFO36_72_EXP=2
NGDBUILD_NUM_FIFO36_EXP=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=64 NGDBUILD_NUM_IBUFDS=8
NGDBUILD_NUM_IBUFGDS=1 NGDBUILD_NUM_IDDR_2CLK=64 NGDBUILD_NUM_IDELAYCTRL=1 NGDBUILD_NUM_INV=69
NGDBUILD_NUM_IODELAY=80 NGDBUILD_NUM_LUT1=12 NGDBUILD_NUM_LUT2=120 NGDBUILD_NUM_LUT3=430
NGDBUILD_NUM_LUT4=161 NGDBUILD_NUM_LUT5=498 NGDBUILD_NUM_LUT6=520 NGDBUILD_NUM_MUXCY=61
NGDBUILD_NUM_MUXF7=40 NGDBUILD_NUM_OBUF=32 NGDBUILD_NUM_OBUFDS=2 NGDBUILD_NUM_OBUFT=64
NGDBUILD_NUM_OBUFTDS=8 NGDBUILD_NUM_ODDR=146 NGDBUILD_NUM_OR2=1 NGDBUILD_NUM_PLL_ADV=1
NGDBUILD_NUM_RAMB36_EXP=1 NGDBUILD_NUM_SRL16E=1 NGDBUILD_NUM_SRLC16E=47 NGDBUILD_NUM_SRLC32E=18
NGDBUILD_NUM_TS_TIMESPEC=1 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=41
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc5vlx50t-1-ff1136 -top=<design_top> -opt_mode=Speed -opt_level=1
-power=NO -iuc=NO -lso="C:/Work/ISE/14/Genesys_MIG/ipcore_dir/mem/example_design/synth/mem.lso" -keep_hierarchy=No
-netlist_hierarchy=As_Optimized -rtlview=Yes -glob_opt=AllClockNets -read_cores=YES
-write_timing_constraints=NO -cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100
-bram_utilization_ratio=100 -dsp_utilization_ratio=100 -reduce_control_sets=Auto -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-use_dsp48=Auto -iobuf=YES -max_fanout=100000 -bufg=32
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Auto
-use_sync_set=Auto -use_sync_reset=Auto -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5