| mem Project Status | |||
| Project File: | test.xise | Parser Errors: | No Errors |
| Module Name: | mem | Implementation State: | Programming File Generated |
| Target Device: | xc5vlx50t-1ff1136 |
|
No Errors |
| Product Version: | ISE 14.7 |
|
1424 Warnings (0 new) |
| Design Goal: | Balanced |
|
All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
|
All Constraints Met |
| Environment: | System Settings |
|
0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slice Registers | 2,802 | 28,800 | 9% | ||
| Number used as Flip Flops | 2,802 | ||||
| Number of Slice LUTs | 1,538 | 28,800 | 5% | ||
| Number used as logic | 1,473 | 28,800 | 5% | ||
| Number using O6 output only | 1,150 | ||||
| Number using O5 output only | 12 | ||||
| Number using O5 and O6 | 311 | ||||
| Number used as Memory | 59 | 7,680 | 1% | ||
| Number used as Shift Register | 59 | ||||
| Number using O6 output only | 59 | ||||
| Number used as exclusive route-thru | 6 | ||||
| Number of route-thrus | 20 | ||||
| Number using O6 output only | 17 | ||||
| Number using O5 output only | 3 | ||||
| Number of occupied Slices | 1,216 | 7,200 | 16% | ||
| Number of LUT Flip Flop pairs used | 3,219 | ||||
| Number with an unused Flip Flop | 417 | 3,219 | 12% | ||
| Number with an unused LUT | 1,681 | 3,219 | 52% | ||
| Number of fully used LUT-FF pairs | 1,121 | 3,219 | 34% | ||
| Number of unique control sets | 153 | ||||
| Number of slice register sites lost to control set restrictions |
271 | 28,800 | 1% | ||
| Number of bonded IOBs | 118 | 480 | 24% | ||
| Number of LOCed IOBs | 118 | 118 | 100% | ||
| IOB Flip Flops | 265 | ||||
| Number of BlockRAM/FIFO | 4 | 60 | 6% | ||
| Number using BlockRAM only | 1 | ||||
| Number using FIFO only | 3 | ||||
| Number of 36k BlockRAM used | 1 | ||||
| Number of 36k FIFO used | 3 | ||||
| Total Memory used (KB) | 144 | 2,160 | 6% | ||
| Number of BUFG/BUFGCTRLs | 4 | 32 | 12% | ||
| Number used as BUFGs | 4 | ||||
| Number of IDELAYCTRLs | 3 | 16 | 18% | ||
| Number of BUFIOs | 8 | 56 | 14% | ||
| Number of DCM_ADVs | 1 | 12 | 8% | ||
| Number of PLL_ADVs | 1 | 6 | 16% | ||
| Average Fanout of Non-Clock Nets | 2.53 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | All Constraints Met | |||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Tue May 26 18:31:03 2015 | 0 | 1404 Warnings (0 new) | 114 Infos (0 new) | |
| Translation Report | Current | Tue May 26 18:31:12 2015 | 0 | 15 Warnings (0 new) | 0 | |
| Map Report | Current | Tue May 26 18:31:50 2015 | 0 | 3 Warnings (0 new) | 14 Infos (0 new) | |
| Place and Route Report | Current | Tue May 26 18:32:23 2015 | 0 | 1 Warning (0 new) | 3 Infos (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | Tue May 26 18:32:33 2015 | 0 | 1 Warning (0 new) | 4 Infos (0 new) | |
| Bitgen Report | Current | Tue May 26 18:33:22 2015 | 0 | 0 | 2 Infos (0 new) | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Current | Tue May 26 18:33:23 2015 | |
| WebTalk Log File | Current | Tue May 26 18:33:28 2015 | |