Device Usage Statistics Report

Device Usage Page (device_usage_statistics.html)

This HTML page displays the device usage statistics that will be sent to Xilinx. The file also contains predefined XML tags used to simplify processing.

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Software Version and Target Device
Product Version:	ISE:10.1.03 (WebPACK)	Target Family:	spartan3e
OS Platform:	NT	Target Device:	xc3s100e
Project ID (random number)	19047.29358.12	Target Package:	cp132
Registration ID	180AANZ9AMJXSWSEX4AMG3EDE	Target Speed:	-5
Date Generated	Sat Mar 28 12:07:17 2009

Device Usage Statistics
Macro Statistics	Miscellaneous Statistics	Net Statistics	Site Usage
Latches=2 1-bit latch=2 ROMs=1 16x7-bit ROM=1 Registers=3 Flip-Flops=3 Counters=3 10-bit up counter=2 29-bit up counter=1 Comparators=2 10-bit comparator less=2	MiscellaneousStatistics AGG_BONDED_IO=44 AGG_IO=44 AGG_SLICE=46 NUM_4_INPUT_LUT=84 NUM_BONDED_IBUF=14 NUM_BONDED_IOB=30 NUM_BUFGMUX=3 NUM_CYMUX=46 NUM_IOB_LATCH=2 NUM_LUT_RT=46 NUM_SLICEL=46 NUM_SLICE_FF=52 NUM_XOR=49	NetStatistics NumNets_Active=168 NumNets_Gnd=1 NumNets_Vcc=1 NumNodesOfType_Active_CLKPIN=30 NumNodesOfType_Active_CNTRLPIN=18 NumNodesOfType_Active_DOUBLE=106 NumNodesOfType_Active_DUMMY=184 NumNodesOfType_Active_DUMMYESC=15 NumNodesOfType_Active_GLOBAL=22 NumNodesOfType_Active_HFULLHEX=3 NumNodesOfType_Active_HLONG=1 NumNodesOfType_Active_HUNIHEX=9 NumNodesOfType_Active_INPUT=233 NumNodesOfType_Active_IOBOUTPUT=14 NumNodesOfType_Active_OMUX=103 NumNodesOfType_Active_OUTPUT=110 NumNodesOfType_Active_PREBXBY=42 NumNodesOfType_Active_VFULLHEX=12 NumNodesOfType_Active_VLONG=3 NumNodesOfType_Active_VUNIHEX=19 NumNodesOfType_Gnd_DOUBLE=2 NumNodesOfType_Gnd_INPUT=4 NumNodesOfType_Gnd_OMUX=2 NumNodesOfType_Gnd_OUTPUT=3 NumNodesOfType_Gnd_PREBXBY=4	SiteSummary BUFGMUX=3 BUFGMUX_GCLKMUX=3 BUFGMUX_GCLK_BUFFER=3 IBUF=14 IBUF_INBUF=14 IBUF_PAD=14 IOB=30 IOB_OFF1=2 IOB_OUTBUF=30 IOB_PAD=30 SLICEL=46 SLICEL_C1VDD=3 SLICEL_CYMUXF=24 SLICEL_CYMUXG=22 SLICEL_F=43 SLICEL_F5MUX=1 SLICEL_FFX=26 SLICEL_FFY=26 SLICEL_G=41 SLICEL_GNDF=21 SLICEL_GNDG=22 SLICEL_XORF=25 SLICEL_XORG=24

Configuration Data
BUFGMUX_GCLKMUX DISABLE_ATTR=[LOW:3] IBUF_PAD IOATTRBOX=[LVCMOS25:14] IOB_OFF1 LATCH_OR_FF=[LATCH:2] OFF1_INIT_ATTR=[INIT0:2]	IOB_PAD DRIVEATTRBOX=[2:10] [12:20] IOATTRBOX=[LVCMOS25:30] PULL=[PULLUP:10] SLEW=[SLOW:30]	SLICEL_FFX FFX_INIT_ATTR=[INIT0:26] FFX_SR_ATTR=[SRLOW:26] LATCH_OR_FF=[FF:26] SYNC_ATTR=[ASYNC:16] [SYNC:10]	SLICEL_FFY FFY_INIT_ATTR=[INIT0:26] FFY_SR_ATTR=[SRLOW:26] LATCH_OR_FF=[FF:26] SYNC_ATTR=[ASYNC:15] [SYNC:11]

Pin Data
BUFGMUX I0=3 I1=1 O=3 S=3 BUFGMUX_GCLKMUX I0=3 I1=1 OUT=3 S=3 BUFGMUX_GCLK_BUFFER IN=3 OUT=3 IBUF I=14 PAD=14 IBUF_INBUF IN=14 OUT=14 IBUF_PAD PAD=14 IOB O1=30 OTCLK1=2 PAD=30 IOB_OFF1 CK=2 D=2 Q=2	IOB_OUTBUF IN=30 OUT=30 IOB_PAD PAD=30 SLICEL BX=4 BY=2 CE=6 CIN=22 CLK=28 COUT=22 F1=43 F2=18 F3=16 F4=13 G1=40 G2=16 G3=16 G4=14 SR=11 X=17 XQ=26 Y=16 YQ=26	SLICEL_C1VDD 1=3 SLICEL_CYMUXF 0=24 1=24 OUT=24 S0=24 SLICEL_CYMUXG 0=22 1=22 OUT=22 S0=22 SLICEL_F A1=43 A2=18 A3=16 A4=13 D=43 SLICEL_F5MUX F=1 G=1 OUT=1 S0=1 SLICEL_FFX CE=5 CK=26 D=26 Q=26 SR=10	SLICEL_FFY CE=6 CK=26 D=26 Q=26 SR=11 SLICEL_G A1=40 A2=16 A3=16 A4=14 D=41 SLICEL_GNDF 0=21 SLICEL_GNDG 0=22 SLICEL_XORF 0=25 1=25 O=25 SLICEL_XORG 0=24 1=24 O=24

Tool Usage

Command Line History

xst -ise <ise_file>
ngdbuild -ise <ise_file> <fname>.ngd
map -ise <ise_file> -intstyle ise -p xc3s100e-cp132-5 -cm area -pr off -k 4 -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
par -ise <ise_file> -w -intstyle ise -ol std -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
trce -ise <ise_file> -intstyle ise -v 3 -s 5 -xml <design> <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
bitgen -ise <ise_file> -intstyle ise -f <fname>.ut <fname>.ncd

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Software Quality
Run Statistics
Program	Runs Started	Runs Finished	Errors	Fatal Errors	Internal Errors	Exceptions	Core Dumps
_impact	17	12	0	0	0	0	0
bitgen	507	506	0	0	0	0	0
map	507	499	0	0	0	0	0
ngdbuild	524	524	0	0	0	0	0
par	499	482	17	0	0	0	0
trce	482	482	0	0	0	0	0
xst	651	648	0	0	0	0	0

Project Statistics
PROP_Synthesis_Tool=XST (VHDL/Verilog)	PROP_Simulator=Modelsim-XE VHDL
PROP_Top_Level_Module_Type=HDL	PROP_PreferredLanguage=VHDL
PROP_Enable_Message_Filtering=false	PROP_Enable_Incremental_Messaging=false
PROP_UseSmartGuide=false	Partitions count=1
FILE_UCF=1	FILE_VHDL=4
PROP_DevFamily=Spartan3E	PROP_DevPackage=cp132
PROP_FitterReportFormat=HTML	PROP_Simulator=Modelsim-XE VHDL
PROP_UserConstraintEditorPreference=Constraints Editor	Project duration(days)=6