2014.4:
 * Version 3.0 (Rev. 2)
 * No changes

2014.3:
 * Version 3.0 (Rev. 2)
 * IP XDC update for timing DRC, no functional changes
 * Clock Inversion in IP top removed for timing DRC, no functional changes.
 * modified to use new sub-cores in place of proc_common. No Functional changes.
 * Updating core to use utils.tcl needed for board flow from common location

2014.2:
 * Version 3.0 (Rev. 1)
 * Repackaged to improve internal automation, no functional changes.
 * Example design XDC update for timing DRC
 * Updated board flow commands in sync with internal flow updates, no functional changes.

2014.1:
 * Version 3.0
 * Improved GUI speed and responsiveness, no functional changes.
 * Added example design
 * Added demonstration testbench
 * Updated synchronizers for clock domain crossing to reduce Mean Time Between Failures (MTBF) from metastability
 * Internal device family name change, no functional changes
 * Virtex UltraScale Pre-Production support.

2013.4:
 * Version 2.0 (Rev. 3)
 * Board support enabled only when board has MII as well as MDIO interfaces.
 * Create clock constraints added to IP XDC
 * Kintex UltraScale Pre-Production support
 * OOC xdc updated to reflect clock period as per user selected frequency in GUI
 * Repackaged to improve internal automation, no functional changes

2013.3:
 * Version 2.0 (Rev. 2)
 * Reduced warnings in synthesis and simulation
 * Enhanced support for IP Integrator
 * Added support for Cadence IES and Synopsys VCS simulators
 * Support for 7-series devices at Production status
 * ID WIDTH is added as a user parameter,should be set to '0' for AXILITE Interface

2013.2:
 * Version 2.0 (Rev. 1)
 * XDC Constraints processing order changed.
 * Added BETA support for future devices.

2013.1:
 * Version 2.0
 * Updated core version for 2013.1 Vivado release. No other functional or interface updates in this release.

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