Zmod Scope Reference Manual

Formerly known as the Zmod ADC.

The Digilent Zmod Scope is an open-source hardware SYZYGY™ ¹⁾compatible pod containing a dual-channel ADC and the associated front end. The Zmod Scope is intended to be used with any SYZYGY™ compatible carrier board having the required capabilities.

The Zmod Scope was designed to be a piece in a modular, HW and SW open-source ecosystem. The Zmod Scope can acquire two signals, with simultaneous sampling. Combined with a SYZYGY™ carrier, other SYZYGY™ compatible pods, Zmod Scope can be used for a variety of applications: data acquisition systems, closed loop controllers, scopes, etc.

• There are multiple members in the Zmod Scope family:
• Zmod Scope 1410-40: 14-bit, 40MSPS
• Zmod Scope 1410-105: 14-bit, 105MSPS
• Zmod Scope 1410-125: 14-bit, 125MSPS
• Zmod Scope 1210-40: 12-bit, 40MSPS
• Zmod Scope 1210-125: 12-bit, 125MSPS
• Zmod Scope 1010-40: 10-bit, 40MSPS
• Zmod Scope 1010-125: 10-bit, 125MSPS

The Zmods in the family are similar, with small loading and performance differences, as explained in the current user manual. In this document, all the members of the family are generically referred as Zmod Scope and only aspects which differ between members are explicitly shown.

This document describes the Zmod Scope's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Zmod Scope, but can help users to design custom configurations for programmable parts in the design.

Zmod Scope's block diagram is presented in Fig. 2 below. The core of the Analog Zmod Scope is a dual channel, high speed, low power ADC, as shown in Table 1. The carrier board is responsible to configure the internal registers of the ADC circuit, provide the acquisition clock and receive the data.

The Analog Input block is also called the Scope, because of similar structure and behavior to such a front end. The signals in this circuitry use a “SC” indexes to indicate they are related to the scope block. Signals and equations also use certain naming conventions. Analog voltages are prefixed with a “V” (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (IN, MUX, BUF, ADC, etc.); to indicate the related instrument (SC, etc.); to indicate the channel (1 or 2); and to indicate the type of signal (P, N, or diff). Referring to the block diagram in Fig. 2 below:

• The Analog Inputs/Scope instrument block includes:
  • Input Divider and Gain Selection: high bandwidth input adapter/divider. High or low-gain can be selected by the FPGA
  • Buffer: high impedance buffer
  • Driver: provides appropriate signal levels and protection to the ADC.
  • Scope Reference: generates and buffers reference voltages for the scope stages
  • ADC: the analog-to-digital converter for both scope channels.
• The Power Supplies and Control block generates all internal supply voltages.
• The MCU works as a I2C memory for two different purposes:
  • The DNA includes the standard SYZYGY™ pod identification information.
  • The Calibration Memory stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Zmod Scope includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The application software uses these parameters to correct the acquired data and the generated signals

In the sections that follow, schematics are not shown separately for identical blocks. For example, the Scope Input Divider and Gain Selection schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation \ref{1} below, $V_{SCOPE-SMA}$ does not contain the channel index (because the equation applies to both channels 1 and 2).

Fig. 3 shows the scope input divider and gain selection stage.

C₅ and C₆ are capacitive trimmers, 3…10pF, -0/+50% tolerance. The worse case range is 4.5…10pF. All other capacitors are 1% tolerance, all the resistors are 0.1%.

The IC1 relay switches between two symmetrical R-C dividers. Each of them provide:

• Scope input impedance = 1MOhm || 18pF
• Two different attenuations for high-gain/low-gain (25:1)
• Controlled capacitance, much higher than the parasitical capacitance of subsequent stages
• Constant attenuation over a large frequency range (trimmer adjusted)

The maximum voltage rating for scope inputs is limited to:

$$-50V<V_{SCOPE-SMA}<50V\label{1}\tag{1}$$

The DC low gain is: $$\frac {V_{SC-LG}}{V_{SCOPE-SMA}}=\frac {R_5}{R_1+R_3+R_5}=0.04\label{2}\tag{2}$$

The High Range (at low gain): $$-25V \le V_{SCOPE-SMA} \le 25V\label{3}\tag{3}$$

The high gain is: $$\frac {V_{SC-HG}}{V_{SCOPE-SMA}} = \frac {R_4 + R_6}{R_2 + R_4 + R_6} = 0.96 \label{4}\tag{4}$$

The Low Range (at high gain): $$-1V \le V_{SCOPE-SMA} \le 1V \label{5}\tag{5}$$

The two dividers are designed to have the same equivalent impedance (both active and reactive):

$$R_{ech} = R_1 + R_3 + R_5 = R_2 + R_4 + R_6 = 1Mohm\label{6}\tag{6}$$

Experiments shown that there are significant parasitic capacities of the layout and buffer input stage: C_PH (high gain divider), parallel to C₆, and C_PL (low gain divider), parallel to C₇. The trimmers should compensate for these parasitic capacities and adjust for perfect matching:

$$C_3*R_2 = (C_{PH} + C_6)*(R_4+R_6)\label{7}\tag{7}$$ $$(C_{PH} + C_6) = \frac{C_3*R_2}{R_4+R_6} = 18pF\label{8}\tag{8}$$

$$(C_4 + C_5)*(R_1 + R_3) = (C_{PL} + C_7)*R_5\label{9}\tag{9}$$ $$(C_{PL} + C_7) = (C_4 + C_5)*\frac{(R_1 + R_3)}{R_5}\label{10}\tag{10}$$

With the chosen values, the correct adjustment results in about mid-position of trimmers C₅ and C₆:

$$C_5 = C_6 = 7pF\label{11}\tag{11}$$

which solves the parasitic capacities as:

$$C_{PH} = 11pF\label{12}\tag{12}$$ $$C_{PL} = 8.8pF\label{13}\tag{13}$$

The Low Gain and High Gain dividers have very close equivalent capacitance, within the tolerances and model approximations:

$$C_{HGech} = \frac{C_3*R_2}{R_2+R_4+R_6} = C_{ech} = 17.28pF\label{14}\tag{14}$$ $$C_{LGech} = \frac{(C_7+C_{PL})*R_5}{R_1+R_3+R_5} = 16.03p\label{15}\tag{15}$$

Experiments show that the equivalent capacitances are even closer than the values above, about 18pF. The computing error mainly derives from trimmer position approximation.

$$C_{ech} = 18p\label{16}\tag{16}$$

The IC2 relay shorts the C1 capacitor when DC coupling is desired. Otherwise, C1 forms a High Pass filter with the selected divider, for AC coupling, with the corner frequency:

$$f_c = \frac{1}{2*\pi*R_{ech}*(C_{ech}+C_{1})} \approx \frac{1}{2*\pi*R_{ech}*C_{1}} = 10.6Hz\label{17}\tag{17}$$

IC1 and IC2 in Fig. 3, are HFD4/4.5L latching relays (possible replacement: IM42GR). The schematic shows the “reset” position. A relay is “set” when a positive voltage is applied at the coil terminals and it is “reset” when a negative voltage is applied (see the polarity on the schematic symbol). The relay keeps state when no current flows trough the coil (the terminals are driven at the same voltage or at least one of the terminals is “open”). The nominal coil voltage is 4.5V.

The IC16, IC17 and IC18 in Fig. 4 are A3910EEETR-T drivers for the relays. They feature:

• Low RDS(on) outputs
• Standby mode with zero current drain
• Small 2 × 2 DFN package
• Crossover Current protection
• Thermal Shutdown protection

Normally, all of them have both HIN and LIN inputs “low” or both “High” driving the “OUT” pins “High Z”. To “set” a relay, OUT2 of IC16 is set “Low” (HIN=“Low”, LIN=“High”) and the corresponding OUT pin of IC17 or IC18 is set “High” (HIN=“High”, LIN=“Low”). All other OUT pins are set “High Z”. To “reset” a relay, OUT2 of IC16 is set “High” (HIN=“High”, LIN=“Low”) and the corresponding OUT pin of IC17 or IC18 is set “Low” (HIN=“Low”, LIN=“High”). All other OUT pins are set “High Z”.

IC14 and IC15 in Fig. 5 are 74LVC07ABQ open-drain gates used as level translators from VADJ = 1.8V to VCC5V0 = 5V.

• 5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic
• Wide supply voltage range from 1.2 V to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
• Inputs accept voltages up to 5 V
• Complies with JEDEC standard:
• JESD8-7A (1.65 V to 1.95 V)
• JESD8-5A (2.3 V to 2.7 V)
• JESD8-C/JESD36 (2.7 V to 3.6 V)
• ESD protection:
• HBM JESD22-A114F exceeds 2000 V
• MM JESD22-A115-B exceeds 200 V
• CDM JESD22-C101E exceeds 1000 V
• Specified from -40 °C to +85 °C and -40 °C to +125 °C

The scope buffer stage provides very high impedance as load for the input divider.

The gain is: $$\frac {V_{BUFF}}{V_{SC-HLG}}=1\label{20}\tag{20}$$

The actual input and output range (for nominal usage) is:

$-1V<V_{SC-HLG}=V_{BUFF}<1V\label{21}\tag{21}$

The scope reference stage generates the 1V reference voltage for the ADC, as well as other internal reference voltages.

$$V_{REFADC}=1V\label{23}\tag{23}$$

The ADC driver is used for:

• Driving the differential inputs of the ADC (with low impedance outputs)
• Providing the common mode voltage for the ADC
• ADC protection.

The Zmod Scope uses a dual channel, high speed, low power, 14-bit, 105MS/s ADC, as shown in Fig. 11.

The differential inputs are driven via a low-pass filter comprised of C114 together with R13, R15, R16, R17 in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by 4 to operate the ADC. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage.

The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V by the SYZYGY™ voltage V_adj.

The multiplexed mode is used, to combine the two channels on a single data bus and minimize the number of used FPGA pins. CLKOUT_SC is provided to the FPGA for synchronizing data.

The nominal differential ADC input voltage range is:

$$-1V<V_{ADC\;diff}<1V\label{33}\tag{33}$$

The total scope gains (from the SMA connectors to the ADC inputs) are:

$$Low \; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=0.038\label{38}\tag{38}$$ $$High \; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=0.91\label{39}\tag{39}$$

Considering the ADC input voltage range shown in \ref{33}:

$$at \; low \; gain: -26.3V<V_{SCOPE-SMA}<26.3V$$ $$at \; high \; gain: -1.1V<V_{SCOPE-SMA}<1.1V\label{40}\tag{40}$$

To cover component value tolerances and to allow software calibration, only the ranges below are specified.

$$at \; low \; gain: -25V<V_{SCOPE-SMA}<25V\label{41}\tag{41}$$ $$at \; high \; gain: -1V<V_{SCOPE-SMA}<1V\label{42}\tag{42}$$

With the 14-bit ADC, the absolute resolution of the scope is (see Table 1):

$$at \; low \; gain: \frac{52.6V}{2^{n}}\label{43}\tag{43}$$ $$at \; high \; gain: \frac{2.12V}{2^{n}}n\label{44}\tag{44}$$

For V_in voltage value at the input of the Scope channel, the Zmod Scope sends a signed n bit integer, N. This value is used to compute V_in:

$$V_{in} = \frac{N \cdot Range \cdot (1+CG)}{2^{n-1}} + CA \label{45}\tag{45}$$

were:

• n = the number of bits (14 for Zmod Scope 14XX, 12 for Zmod Scope 12XX, 10 for Zmod Scope 10XX)
• N = the n bit, 2's complement integer number returned by the ADC
• V_in= the corrected value of the input voltage
• CA = calibration Additive constant (for the appropriate channel and gain; see Table 4)
• CG = calibration Gain constant (for the appropriate channel and gain; see Table 4)
• Range= the ideal Range of the Scope input stage (approximation of the values in equation \ref{40}):
  • 1.086 (for low range: ±1V) or
  • 26.25 (for high range: ±25V)

Fig. 12 shows a typical spectral characteristic of the scope input stage. A PXIe-5433 80 MHz Function/Arbitrary Waveform Generator was used to generate the input signal of 0.9V, for High Gain Scale, respectively 10V for the Low Gain scale. A Tektronix DPO5204B scope was used for measuring the reference signal (at the scope SMA connector) and the output signal (at the input of the ADC). A differential probe was used to read the output signal on the pads of the unloaded C115. The signal swept from 800kHz to 80MHz. The effective values of the input and output signals were recorded for each frequency. The measurements were further processed to display the input stage frequency characteristics, as shown in Fig. 10.

For Zmod Scope XXXX-100MHz and Zmod Scope XXXX-125MHz, for both scales, the 3dB bandwidth is 70MHz+. The 0.5dB bandwidth is 30MHz and the 0.1dB bandwidth is 20MHz. For Zmod Scope XXXX-40MHz, for both scales, the 3dB bandwidth is 20MHz+. The 0.5dB bandwidth is 8MHz and the 0.1dB bandwidth is 4MHz

The standard -3dB bandwidth definition is derived from filter theory. At cutout frequency, the scope attenuates the spectral components by 0.707, assuming an error of ~30%, way too high for a measuring instrument. The bandwidth with a specified flatness is useful to better define the scope spectral performances. The bandwidth @ 0.5dB, means a flatness error of a max 5.6%, while bandwidth @ 0.1dB means flatness error of a max 1.1%.

The ATtinny44 MCU in Fig. 13 works as a I2C memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing.

The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as “read-only”. The User Calibration Coefficients are stored in the EEPROM memory of the MCU, which is write-protected via a magic number at a magic address. The memory structure can be consulted below.

• Program Memory Type: Flash
• Program Memory Size (KB): 4
• CPU Speed (MIPS/DMIPS): 20
• SRAM Bytes: 256
• Data EEPROM/HEF (bytes): 256
• Digital Communication Peripherals: 1-SPI, 1-I2C
• Capture/Compare/PWM Peripherals: 1 Input Capture, 1 CCP, 4PWM
• Timers: 1 x 8-bit, 1 x 16-bit
• Number of Comparators: 1
• Temperature Range (C): -40 to 85
• Operating Voltage Range (V): 1.8 to 5.5
• Pin Count: 14
• Low Power: Yes

The Zmod Scope is compliant with SYZYGY™ Specification. It contains an MCU able to calculate the Geographical Address and provide the DNA information via I2C. The DNA is stored in the MCU FLASH at the address range: 0x8000 - 0x80FF with the following structure:

The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, capacitance, offsets, bias currents, etc.) as typical values and tolerances. The equations in previous chapters consider typical values. Component tolerances affect DC and AC performances of the Zmod Scope. To minimize these effects, the design uses:

• 0.1% resistors and 1% capacitors in all the critical analog signal paths
• Capacitive trimmers for balancing the Scope Input Divider and Gain Selection
• No other mechanical trimmers (as these are big, expensive, unreliable and affected by vibrations, aging, and temperature drifts)
• Software calibration, at manufacturing
• User software calibration, as an option

A software calibration is performed on each device as a part of the manufacturing test. Reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod Scope device, both as Factory Calibration Data and User Calibration Data. The WaveForms software allows the user performing an in-house calibration and overwrite the User Calibration Data. Returning to Factory Calibration is always possible.

The Software reads the calibration parameters from the Zmod Scope MCU via the I2C bus and uses them to correct the acquired signals. The structure of the calibration data is shown below:

At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write a any other number to the magic address.

This block includes the internal power supplies.

The Zmod Scope gets the digital rails from the carrier board, via the SYZYGY connector:

• VCC5V0 - used for relays and analog supplies
• VCC3V3 - used for the MCU and analog supplies
• Vadj = 1.8V - used for the ADC digital rail

The internal analog rails sequence is:

• AVCC1V8 - ADC analog rail
• AVCC3V0 - ADC driver
• AVCC-2V5, AVCC4V5 - Scope buffer, reference voltage

The analog supply AVCC1V8 is built from VCC5V0 using IC21, an ADP2138 Fixed Output Voltage, 800mA, 3MHz, Step-Down DC-to-DC converter. To insure low output voltage ripple a second LC filter (FB9 in Fig. 9) is added and forced PWM mode is selected.

• Input voltage: 2.3 V to 5.5 V
• Peak efficiency: 95%
• 3 MHz fixed frequency operation
• Typical quiescent current: 24 μA
• Very small solution size
• 6-lead, 1 mm × 1.5 mm WLCSP package
• Fast load and line transient response
• 100% duty cycle low dropout mode
• Internal synchronous rectifier, compensation, and soft start
• Current overload and thermal shutdown protections
• Ultra-low shutdown current: 0.2 μA (typical)
• Forced PWM and automatic PWM/PSM modes

The analog supply AVCC3V0 is built from VCC3V3 using IC22, an ADP122 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Fixed Output Voltage. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB3 in Fig. 10, FB6 (Channel 2 ADC Driver - not shown), FB7 in Fig. 7.

• Input voltage supply range: 2.3 V to 5.5 V
• 300 mA maximum output current
• Fixed and adjustable output voltage versions
• Very low dropout voltage: 85 mV at 300 mA load
• Low quiescent current: 45 µA at no load
• Low shutdown current: <1 µA
• Initial accuracy: ±1% accuracy
• Up to 31 fixed-output voltage options available from
• 1.75 V to 3.3 V
• Adjustable-output voltage range
• 0.8 V to 5.0 V (ADP123)
• Excellent PSRR performance: 60 dB at 100 kHz
• Excellent load/line transient response
• Optimized for small 1.0 μF ceramic capacitors
• Current limit and thermal overload protection
• Logic controlled enable
• Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP

The analog supply AVCC4V5 is built from VCC5V0 using IC19, an ADP123 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Adjustable Output Voltage. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB2 in Fig. 6, FB5 (Channel 2 ADC Buffer - not shown), FB8 in Fig. 9.

• Input voltage supply range: 2.3 V to 5.5 V
• 300 mA maximum output current
• Fixed and adjustable output voltage versions
• Very low dropout voltage: 85 mV at 300 mA load
• Low quiescent current: 45 µA at no load
• Low shutdown current: <1 µA
• Initial accuracy: ±1% accuracy
• Up to 31 fixed-output voltage options available from
• 1.75 V to 3.3 V
• Adjustable-output voltage range
• 0.8 V to 5.0 V (ADP123)
• Excellent PSRR performance: 60 dB at 100 kHz
• Excellent load/line transient response
• Optimized for small 1.0 μF ceramic capacitors
• Current limit and thermal overload protection
• Logic controlled enable
• Compact packages: 5-lead TSOT and 6-lead 2 mm × 2 mm LFCSP

The AVCC-2V5 analog power supply is implemented with the ADP2301 Step-Down regulator in an inverting Buck-Boost configuration. See application Note AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB1 in Fig. 6, FB4 (Channel 2 ADC Buffer - not shown). The ADP2301 features:

• 1.2 A maximum load current
• ±2% output accuracy over temperature range
• 1.4 MHz switching frequency
• High efficiency up to 91%
• Current-mode control architecture
• Output voltage from 0.8 V to 0.85 × VIN
• Automatic PFM/PWM mode switching
• Integrated high-side MOSFET and bootstrap diode,
• Internal compensation and soft start
• Undervoltage lockout (UVLO), Overcurrent protection (OCP) and thermal shutdown (TSD)
• Available in ultrasmall, 6-lead TSOT package

The SYZYGY™ connector in provides the interface with the carrier board. The used signals are:

• Power rails
  • VCC5V0
  • VCC3V3
  • VADJ - needs to be set by the carrier board to 1.8V
  • GND
  • Shield
• SYZYGY™ I2C bus:
  • MCU_SCLUSCK
  • MCU_SDA_MOSI
• ADC differential input clock
  • CLKIN_ADC_P
  • CLKIN_ADC_N
• ADC single ended output clock:
  • CLKOUT_ADC (coupled with GND in the differential P2C pair)
• R_GA for geographical address identification
• SYNC_ADC for ADC internal clock divider synchronization
• ADC data bus: DOUT_ADC_0…13
• ADC SPI bus:
  • CS_SC1n
  • SCLK_SC
  • SDIO_SC
• relay control
  • SCx_yy_z

Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania