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Hidden because it was decided not to publish this update procedure.

====== How to Adapt a Board File Based Project for ZedBoard Rev E with 1 GB RAM ======

===== Introduction =====
Some articles of the revision E ZedBoard development boards have 1 GB total DDR3 memory; all of the previous revisions have 512 MB DDR3 memory. The memory part change makes Rev. E boards incompatible with the already built projects for the ZedBoard such as demos and reference projects due to the configuration targeting a different memory part. 

This guide will describe how to change the DDR3 memory part configuration and re-build existing projects.

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===== Identifying Affected Boards =====
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Only some articles of Rev. E ZedBoards are affected. These boards are loaded with a 4 Gb (32 Meg x 16 x 8) instead of 2 Gb (16 Meg x 16 x 8) DDR3 chips.

The 4 Gb parts on some Rev. E boards correspond to a Micron part number of MT41x256M16, whereas 2 Gb parts on previous revisions of the ZedBoard have a Micron part number of MT41x128M16. To readily determine which part is loaded on a ZedBoard, find the FBGA code printed on the DDR memory (located to the left of IC16, the Zynq 7020 chip) and search it on Micron's FBGA Decoder tool, https://www.micron.com/support/tools-and-utilities/fbga.

If the memory is revealed to match the 4 Gb part number of MT41x256M16, follow the rest of this document to update the memory part in existing ZedBoard materials. ZedBoards with the 2 Gb part do not require any updates to existing projects.
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{{ :reference:programmable-logic:zedboard:zedboardddr3_fbga_code.png?600 | Example location of FBGA code on DDR3 memory}}
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===== Inventory =====
  * ZedBoard Rev. E with 1 GB DDR3 memory (MT41K**256**M16TW-107),
    * USB Programming cable, USB UART cable, and a 12 V Power Supply, as required by the ZedBoard
  * Any hardware component required by the project you want to update (e.g. Pmods, FMC module, etc.),
  * Vivado + SDK/Vitis (Use the version that the original project was built in).
    * See [[reference/programmable-logic/guides/installation|Installing Vivado, Vitis, and Digilent Board Files]] for instructions on how to install these tools. 
    * An older tutorial that installs Xilinx SDK is available [[vivado/installing-vivado/start|here]].

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===== Update Procedure =====
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Open the project to be updated in the correct version of Vivado. 

Open the existing Block Design.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_openBlockDesign.png?600 | Open the existing Block Design}}
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Locate the Zynq IP in the Block Diagram.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_ZynqIP_BlockDiagram.png?600 | Find the Zynq IP}}
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Re-customize the Zynq7 Processing System IP by double clicking on the Zynq IP.

Navigate to the DDR Configuration from the Page Navigator.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_recustomizeIP.png?600 | Re-customize the Zynq IP}}
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Change the memory part to MT41K256M16 RE-125.

Click **OK**.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_changeDDR.png?600 | Change the DDR3 memory part}}
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Validate the new design by clicking the **Validate Design** button ({{:learn:programmable-logic:tutorials:2020.1:validate-block-design:validate-button.png|}}) in the Diagram pane's toolbar (or press the F6 key).

After the design has been successfully validated, click **OK**. Save the block design.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_ValidateDesign.png?600 | Validate the design}}
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Generate the Bitstream by clicking the **Generate Bitstream** button in the //Program and Debug// section of the //Flow Navigator// pane on the left side of the window.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_GenerateBitstream.png?600 | Re-generate the bitstream}}
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After the bitstream has generated, export the hardware design by clicking **Export → Export Hardware** in the //File// menu.
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{{ :learn:programmable-logic:tutorials:2020.1:export-fixed-hardware:export-hardware.png?600 | Export the Hardware design}}
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--> Vivado 2019.2 or later #
If you are using Vivado 2019.2 or later
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Use the //Fixed// platform and click **Next**.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_FixedPlatform.png?600 | Select the Fixed Platform type}}
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Select //Include Bitstream// and click **Next**.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_includeBitstream.png?600 | Include the Bitstream the exported Hardware Platform}}
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Save the hardware platform (the Xilinx Shell Architecture, or XSA file) to a known folder. For some Digilent projects, the hw_handoff folder is used, though this specific folder is not required.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_hw_handoff.png?600 | Put your .xsa in an easily findable location}}
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Open the already existing project in Vitis and Right Click on the platform project (the green one without a //_system// appended at the end of the name) and select //Update Hardware Specification//.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_Vitis_hwSpecification.png?600 | Update the Hardware Specification}}
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Provide the location of the .xsa file created earlier and click **OK**.
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{{ :reference:programmable-logic:zedboard:ZedboardDDR3_Vitis_hwPath.png?600 | Find and select the updated hardware platform}}
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<--

--> Vivado 2019.1 or earlier #
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*/