~~NOTOC~~ 
    
====== Virtex-II Pro ======
{{Digilent Infobox
| Manual = [[reference-manual]]
| Support = https://forum.digilentinc.com/forum/4-fpga/
| Title = Virtex-II Pro
| Subtitle = Development System
| Header = Key Specifications
| Logic Cells = 30,816
| BRAM = 2,448Kb
| DDR = Up to 2GB of DDR SDRAM
| Ethernet = On-board 10/100 Ethernet PHY
| Clocks = 100MHz system clock, 75MHz SATA
| Header = Connectivity and On-board I/O
| RS-232 = RS-232 DB9 serial port
| PS/2 = Two PS-2 serial ports
| Audio = AC-97 audio CODEC with audio \\ amplifier and speaker/headphone \\ output and line level output
| Microphone = Microphone and line \\ level audio input
| Video = On-board XSGA output, up to \\ 1200 x 1600 at 70Hz refresh
| Switches = 4
| Push-buttons = 5
| LEDs = 4 LEDs
| User LED = 4
| User RGB LED = 4
| Header = Electrical
| Power = 4.5-5.5V 
| Logic Level = 3.3V
| Header = Physical
| Width = x in
| Length = y in
| Header = Design Resources
| Master UCF = {{:reference:programmable-logic:virtex-ii-pro:ucf_files.zip| }}
| Header = Documentation
| Primary IC = Virtex-II Pro (XC2VP30)
| Schematic = {{:reference:programmable-logic:virtex-ii-pro:xupv2p-sch.pdf| }}
| Base System Builder Guide = {{:reference:programmable-logic:virtex-ii-pro:xupv2p_base_system_builder.pdf| }}
| User Guide = {{:reference:programmable-logic:virtex-ii-pro:xupv2p_user_guide.pdf| }}
}}

{{page>reference-manual}} \\ \\
 
===== Tutorials =====
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{{topic>virtex-ii-pro +tutorial}}


===== Example Projects =====
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{{topic>virtex-ii-pro +project}}

===== Additional Resources =====
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== Demo Projects ==
  * Edge Detection -- {{virtex-ii:conv5x5_matlab_jtag_xup_hw_in_loop.zip|ZIP}}
  * Ethernet MAC OneWire -- {{virtex-ii:xup_bsb_emac_onewire.zip|ZIP}}
  * OneWire -- {{:virtex-ii:xup_bsb_onewire.zip|ZIP}}
  * PS2 -- {{:virtex-ii:xup_bsb_ps2.zip|ZIP}}
  * MicroBlaze uClinux -- {{:virtex-ii:uclinux-xupv2p_rev_1_1.zip|ZIP}}

== VGA ==
  * VGA SlideShow (with 256MB RAM) -- {{:virtex-ii:slideshow_256mb.zip|ZIP}}
  * 512 MB Dual Rank DDR Memory with VGA controller -- {{:virtex-ii:xup_bsb_512m_dual_rank_vga_rev_1_1.zip|ZIP}}
  * 512 MB Single Rank DDR Memory with VGA controller -- {{:virtex-ii:xup_bsb_512m_single_rank_vga_rev_1_1.zip|ZIP}}
  * 256 MB Single Rank DDR Memory with VGA controller -- {{:virtex-ii:xup_bsb_256mb_single_rank_vga_rev_1_1.zip|ZIP}}


== Built In Projects ==
  * Built in Self Test (BIST) -- {{:virtex-ii:bist_rev_1_5.zip|ZIP}}
  * Built In Demo -- {{:virtex-ii:built_in_demo_rev_1_1.zip|ZIP}}
=== Demonstration Projects ==
  * Video Capture (with VDEC1) -- {{:virtex-ii:video_capture_rev_1_1.zip|ZIP}}
  * XUP-V2Pro Pack -- {{:virtex-ii:edk-xup-v2propack.zip|ZIP}}
  * Using High Speed Serial MGTs with the Aurora IP -- {{:virtex-ii:xupv2p_aurora.zip|ZIP}}
  * JTAG Hardware CoSIm with System Generator for DSP -- {{:virtex-ii:jtag_cosim.zip|ZIP}}

{{tag>programmable-logic programmable-logic-start virtex-ii-pro resource-center}}