~~TechArticle~~ ====== Add a Microblaze Processor to a Block Design ====== The Microblaze soft-core processor IP can be used to instantiate a processor within your FPGA design. This processor can be very useful for controlling and configuring hardware components. This section discusses how you can add a Microblaze processor and several useful components, including UART for standard output and DDR memory support, to your block design. **Note:** //This section is intended for use with boards without a Zynq chip. For Zynq boards, the Zynq7 Processing System should be used instead.// **Note:** //If you aren't sure whether your board has DDR memory, check the //Memory// column of the specification table on this site's [[programmable-logic:start]] page.// --> Follow the steps in this dropdown for boards without DDR memory # First, an external clock should be added to the block design, so that it can be used to generate any other clocks required by the design. Open the **Board** tab, and find the system clock. Right-click on it and select **Connect Board Component**. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-1.png?600 |}} ---- In the //Connect Board Component// dialog, select the CLK_IN1 of a new Clocking Wizard IP. This will add a clocking wizard to the design, which can be used to easily configure the board's MMCMs and PLLs to generate any required clocks. Click **OK** to continue. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-2.png?600 |}} ---- Next, an external reset port should be added to the design that can be used to reset the entire system. Click the **Run Connection Automation** button in the green //Designer Assistance// toolbar. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-3.png?600 |}} ---- In the //Run Connection Automation// dialog, in the list on the left side of the dialog, make sure that the Clocking Wizard's reset box is checked. The //Select Board Part Interface// dropdown lists any options for resets that are specified in your board's board files. For most boards, only one option will be available. Click **OK** to continue. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-4.png?600 |}} ---- **Note:** //Depending on the polarity of the reset button (active high or active low), a //Utility Vector Logic// IP may be inserted between the reset port and the Clocking Wizard. This is used to ensure that the active high reset pin of the IP is provided with the correct polarity of reset signal, and that the design will not be held in reset while the reset button is not pressed.// {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-5.png?600 |}} ---- Your design will require at least one clock from the clocking wizard. If your design requires more clocks, then they must be added through the Clocking Wizard. Double click on the Clocking Wizard IP core to edit its settings. Navigate to the //Output Clocks// tab. Additional clocks are added to the Clocking Wizard by checking a box in the //Output Clock// column, and specifying a //Requested Output Frequency//. Additionally, if desired, the ports can be named according to their intended purpose. If your design requires additional clocks (such as for an ext_spi_clock pin), they should be added now. Click **OK** to confirm your changes to the Clocking Wizard's settings. If you aren't sure that you have all of the clocks you need, don't worry, you can always come back and add them by reconfiguring this IP. This task can be performed whenever in the design process it becomes necessary. {{ :reference:programmable-logic:guides:microblaze-8.png?600 |}} ---- Next, use the **Add IP** button ({{:learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-ip.png?nolink|}}) to add the //MicroBlaze// IP to the design. The block that is added represents the core of the Microblaze processor. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-12.png?600 |}} ---- Next, block automation will be run so that additional supporting infrastructure can be added to the design. Click **Run Block Automation** in the green //Designer Assistance// bar. **Note:** //The screenshot to the right is not representative for a design not using DDR, as these designs will not contain a MIG IP core.// {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-13.png?600 |}} ---- In the //Run Block Automation// dialog, several settings can be specified for how the Microblaze IP will be connected to the rest of the design: * **Local Memory** specifies how much block RAM memory will be dedicated to the processor. DDR-less designs require more memory, and the amount of memory necessary depends heavily on the size of the software application being run. 32KB is enough for many small applications. * **Cache Configuration** can help the speed of designs using DDR memory. It should be enabled when using DDR and disabled otherwise. * **Debug Module** allows you to specify the capabilities of the debugger. The default //Debug Only// option is recommended. * **Peripheral AXI Port** enables or disables the AXI master interface of the processor. It must be enabled to allow the processor to be connected to hardware peripherals. * **Interrupt Controller** specifies whether the processor can be interrupted by its peripherals. Whether or not it needs to be enabled depends on your design requirements. If any IP that you intend to connect to the processor must have interrupts to function correctly, the box must be checked. * **Clock Connection** specifies the processor's clock. Designs using DDR should use the MIG's ui_clk pin, while designs without DDR should use the Clocking Wizards clk_out1 pin. **Note:** //Settings not present in this list are out of the scope of this guide, and can safely be left as their default.// Confirm that the settings meet your design requirements. It should be noted that while it is possible to change these settings manually later (for example, by manually adding an AXI INTC IP and connecting it to the processor), the easiest way to do so will be to clear the Microblaze processor out of your block design and restart the process of adding the processor. This is to say, the settings chosen here are important. Getting them right the first time will save you time in the long run. Click **OK** to continue. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-14.png?600 |}} ---- Next, in order for the software design to be able to print to a serial console on a host computer, a UART peripheral must be connected. Find the //USB UART// interface in the //Board// tab, right click on it, and select **Connect Board Component**. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-18.png?600 |}} ---- In the dialog that pops up, select a new AXI Uartlite IP's UART interface, and click **OK** to add the block to the diagram. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-19.png?600 |}} ---- To connect all remaining AXI cores that have not yet been connected to the processor, click the **Run Connection Automation** button in the green //Designer Assistance// bar. Check the //All Automation// box in the list on the left side of the window to select all of the remaining AXI cores. The dropdown settings available for each core can safely be left as their default values. Click **OK** to automatically connect them to the processor. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-20.png?600 |}} <-- --> Follow the steps in this dropdown for boards with DDR memory # {{section>microblaze-adding-ddr#add_the_mig_ip&noheader}} {{section>microblaze-adding-ddr#mig_clocking&noheader}} {{section>microblaze-adding-ddr#mig_reset&noheader}} {{section>microblaze-adding-ddr#other_mig_ports&noheader}} {{section>microblaze-adding-ddr#additional_clocks&noheader}} {{section>microblaze-adding-ddr#mig_success&noheader}} ---- Next, use the **Add IP** button ({{:learn:programmable-logic:tutorials:2020.1:add-zynq-processor:add-ip.png?nolink|}}) to add the //MicroBlaze// IP to the design. The block that is added represents the core of the Microblaze processor. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-12.png?600 |}} ---- Next, block automation will be run so that additional supporting infrastructure can be added to the design. Click **Run Block Automation** in the green //Designer Assistance// bar. **Note:** //The screenshot to the right is not representative for a design not using DDR, as these designs will not contain a MIG IP core.// {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-13.png?600 |}} ---- In the //Run Block Automation// dialog, several settings can be specified for how the Microblaze IP will be connected to the rest of the design: * **Local Memory** specifies how much block RAM memory will be dedicated to the processor. DDR-less designs require more memory, and the amount of memory necessary depends heavily on the size of the software application being run. 32KB is enough for many small applications. * **Cache Configuration** can help the speed of designs using DDR memory. It should be enabled when using DDR, and disabled otherwise. * **Debug Module** allows you to specify the capabilities of the debugger. The default //Debug Only// option is recommended. * **Peripheral AXI Port** enables or disables the AXI master interface of the processor. It must be enabled to allow the processor to be connected to hardware peripherals. * **Interrupt Controller** specifies whether the processor can be interrupted by its peripherals. Whether or not it needs to be enabled depends on your design requirements. If any IP that you intend to connect to the processor must have interrupts to function correctly, the box must be checked. * **Clock Connection** specifies the processor's clock. Designs using DDR should use the MIG's ui_clk pin, while designs without DDR should use the Clocking Wizards clk_out1 pin. **Note:** //Settings not present in this list are out of the scope of this guide, and can safely be left as their default.// Confirm that the settings meet your design requirements. It should be noted that while it is possible to change these settings manually later (for example, by manually adding an AXI INTC IP and connecting it to the processor), the easiest way to do so will be to clear the Microblaze processor out of your block design and restart the process of adding the processor. This is to say, the settings chosen here are important. Getting them right the first time will save you time in the long run. **Important!** When working with multiple clocks in a design (as happens to always be the case when working with the MIG) it is important to verify that you are picking the correct //Clock Connection// from the dropdown. In the screenshot to the right, the 100 MHz clk_out1 from a clocking wizard is chosen. You may instead wish to run your design off of ui_clk itself. Do not select the system clock input to the MIG. Click **OK** to continue. {{ :programmable-logic:guides:block-automation.png?600 |}} ---- Next, the MIG's AXI interface must be connected to Microblaze's cache ports, in order to allow data to move back and forth between processor and DDR memory. {{section>microblaze-adding-ddr#connect_the_mig_to_the_microblaze_processor}} ---- Next, in order for the software design to be able to print to a serial console on a host computer, a UART peripheral must be connected. Find the //USB UART// interface in the //Board// tab, right click on it, and select **Connect Board Component**. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-18.png?600 |}} ---- In the dialog that pops up, select a new AXI Uartlite IP's UART interface, and click **OK** to add the block to the diagram. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-19.png?600 |}} ---- To connect all remaining AXI cores that have not yet been connected to the processor, click the **Run Connection Automation** button in the green //Designer Assistance// bar. Check the //All Automation// box in the list on the left side of the window to select all of the remaining AXI cores. The dropdown settings available for each core can safely be left as their default values. Click **OK** to automatically connect them to the processor. {{ :learn:programmable-logic:tutorials:2020.1:add-microblaze-processor:microblaze-20.png?600 |}} <-- ----