====== Getting Started with Microblaze Servers ====== **Note:**The Nexys Video uses a Gigabit Ethernet module which requires the TEMAC IP that is **not contained in the Vivado Webpack**. In order to complete this tutorial, you must either purchase a license for the TEMAC IP or get the evaluation license for free from their website by following [[vivado:temac|this guide]]. ===== Description ===== This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the [[gsmb|Getting Started with Microblaze]] guide by making use of the on-board Ethernet port and GPIOs for the Nexys Video FPGA board. At the end of this tutorial you will have a comprehensive hardware design for Nexys Video that makes use of various Hardware ports on the Nexys Video which are managed by the Microblaze Softcore Processor block. ===== What you need before proceeding with this guide ===== ==== Software ==== * Xilinx Vivado with the SDK package. * Follow this Wiki guide ([[vivado:installation|Installing Vivado]] ) on how to install and activate Vivado 2014.4 * TEMAC IP license installed * Follow this Wiki guide ([[vivado:temac|Installing the 120 Day Evaluation License for the TEMAC IP]]). ==== Board Support Files ==== * Board Support Files. These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks. * Follow this Wiki guide ([[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] ) on how to install Board Support Files for Vivado 2014.4. **The Nexys Video {{https://github.com/Digilent/vivado-boards/tree/master/new/board_files/nexys_video/A.0|board files}}** ==== Hardware ==== * Digilent Nexys Video FPGA Board and Micro USB Cable for UART communication and JTAG programming ----- ===== Introduction ===== Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server. ----- ===== General Design Flow ===== I. Vivado * Open Vivado and select Nexys Video board * Create an new Vivado Project * Create empty block design workspace inside the new project * Add required IP blocks using the IP integrator tool and build Hardware Design * Validate and save block design * Create HDL system wrapper * Run design Synthesis and Implementation * Generate Bit File * Export Hardware Design including the generated bit stream file to SDK tool * Launch SDK Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado. II. SDK * Create new application project and select default Hello World template * Program FPGA * Run configuration by selecting the correct UART COM Port and Baud Rate ----- ===== Step- by- Step Walk Through ===== ==== Create a new project ==== 1. Click on Create New Project. Choose the Project Name and Location such that there are **no blank spaces**. This is an important naming convention to follow for project names, file names and location paths. Underscore in a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/Vivado_Projects. Name your Project and select the Project location and click next. 2. Choose Project Type as RTL Project. Leave the - do not specify sources box unchecked and click next. 3. If you have followed the Board Support File Wiki guide then click next and select **Boards**. From the filter options make required selections for Vendor, Display Name and Board Revision. **Nexys Video** should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. {{:nexys:nexysvideo:2.jpg?nolink|}} 4. Click Next, followed by Finish and Vivado will create a project for you. ==== Create a Block Design ==== 5. Create a Block Design by clicking the button circled in blue below. {{:nexys4-ddr:server_1.jpg?nolink|}} ==== Add the Microblaze Core ==== 6. Start out by clicking the //"Add IP"// button circled in blue below. Search for //"Microblaze"// and double click the IP highlighted below. {{:nexys4-ddr:server_2.jpg?nolink|}} 7. Click "Run Block Automation" circled in blue, and change the options to match the ones in the picture below. Click "Ok". {{:nexys:nexysvideo:4.jpg?nolink|}} ==== Adding the Necessary Output Clocks ==== 8. Double-click the //Clocking Wizard// block highlighted below, and set CLK_IN1 to use "sys_clock" and EXT_RESET_IN to use "reset". {{:nexys4-ddr:server_4.jpg?nolink|}} 9. Select the Output Clocks tab and enable //clk_out2//, //clk_out3//. Set //clk_out2// to **200MHz**, and //clk_out3// to **125MHz**. Set the Reset Type to **Active Low** using the bullets below. When you are finished, click Ok. {{:nexys:nexysvideo:6.jpg?nolink|}} ==== Adding More Interrupts ==== 10. Find the //Concat// block and double click it. Set number of ports to 5 and press OK. {{:nexys:nexysvideo:5.jpg?nolink|}} ==== Adding the IP Cores ==== 11. We will now add all of the necessary IP blocks to our project. There are 4 cores we will add: * Memory Interface Generator * AXI Uartlite * AXI Ethernet Subsystem * AXI Timer Add all of these to your design, one at a time, using the //"Add IP"// button. Once they are all added, you should see the four blocks shown below. {{:nexys:nexysvideo:7.jpg?nolink|}} ==== Configuring and Routing the IP Cores ==== 12. Click //"Run Block Automation"// and run it for the **mig_7series_0** block. {{:nexys:nexysvideo:8.jpg?nolink|}} When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys Video. Click OK to dismiss this message. You will find the MIG IP block now has additional input and output pins which have to be connected to valid signals. {{:nexys4-ddr:mig_27-2.jpg?nolink|}} 13. Click //"Run Block Automation"// and run it for the **axi_ethernet_0** block. Change //Physical Interface Selection// to **RGMII** and click OK. {{:nexys:nexysvideo:9.jpg?nolink|}} Click //"Run Connection Automation"//. Un-check the **microblaze_0** check-box and click OK. {{:nexys:nexysvideo:10.jpg?nolink|}} 14. Click //"Run Connection Automation"// again. Run this for the **axi_ethernet_0_dma**. {{:nexys:nexysvideo:11.jpg?nolink|}} 15. Click //Regenerate Layout// (circled in blue below), and your block design should look like this: {{:nexys:nexysvideo:12.jpg?nolink|}} ==== Routing the Missing Connections ==== 16. The //Concat// block takes interrupt inputs and sends them to the Microblaze controller. {{:nexys:nexysvideo:concat.jpg?nolink&200|}} **Route the following connections to the inputs of the //Concat// block.** Order does not matter. * **interrupt** on the //AXI Timer// block. * **mm2s_introut** and **s2mm_introut** on the //axi_ethernet_0_dma// block. * **mac_irq** and **interrupt** on the //axi_ethernet_0// block. {{:nexys:nexysvideo:13.jpg?nolink|}} 17. * Connect **resetn** on the //Clocking Wizard// block to the **reset** pin input. {{:nexys4-ddr:server_14.jpg?nolink|}} 18. * Connect **sys_clk_i** on the //mig_7_series_0// block to the **clk_out2** output from the //Clocking Wizard//. {{:nexys:nexysvideo:14.jpg?nolink|}} 19. Right click on the blue striped rectangle next to the **DDR3+** bus on the //Memory Interface Generator// block and click //"Make External"//. {{:arty:9.jpg?nolink|}} 20. Clicking //Regenerate Layout// again will result in your final block design layout for this project. {{:nexys:nexysvideo:15.jpg?nolink|}} 21. Click the **Validate Design** {{:nexys:nexysvideo:validate.jpg?nolink|}} button to make sure that you did not make any errors. 22. Now, right click on your design_1 block diagram and click //"Create HDL Wrapper"//. When the window pops up, select the "Let Vivado manage wrapper and auto-update" bullet and click OK. {{:nexys4-ddr:server_22.jpg?nolink|}} 23. Click "Generate Bitstream" at the top of the work space. This process will take a while. {{:nexys4-ddr:server_23.jpg?nolink|}} ==== Exporting Hardware Design to SDK ==== 24. On the top left corner of the window, from the tool bar click on //File// and select //Export Hardware//. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. **Make sure the generated bitstream is included by checking the box**. {{:nexys4-ddr:server_24.jpg?nolink|}} ==== Launching SDK ==== 25. Go to //File// and select //Launch SDK// and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete. {{:vivado:mig_45.jpg|}} ==== Inside SDK for Vivado ==== 26. A new window for SDK will open. The HW design specification and included IP blocks are displayed in the //system.hdf// file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory. Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK. Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server. {{:vivado:mig_46.jpg|}} ==== Creating New Application Project in SDK ==== 27. Go to //File// in the main tool bar and select **New >> Application Project**. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure the //Target Hardware// is the correct hardware design. In our case, it will be "design_1_wrapper_hw_platform_0". If for example, you also have another hardware design in the //Project Explorer// window, then you will also see this design name in the Target Hardware drop down selection list. Since we only have one hardware design **design_1_wrapper_hw_platform_0** this will be our target hardware. Select **Create New** under **Board Support Package**. The tool will automatically populate the **Board Support Package** name to match with the give project name. Click Next. {{:nexys4-ddr:server_25.jpg?nolink|}} Select //IwIP Echo Server// under the list of available templates and click Finish. {{:nexys4-ddr:server_26.jpg?nolink|}} 28. After completing the previous step, you will see two new folders in the //Project Explorer// panel. * **echo_server** which contains all the binaries, .C and .H (Header) files * **echo_server_bsp** which is the board support folder **echo_server** is our main working source folder. This also contains an important file shown here in the src folder called "lscript.ld". This is a Xilinx auto generated linker script file. Double click on this file to open. ==== Verify Linker Script File for Memory Region Mapping ==== 29. In the linker script, take a look at the **Section to Memory Region Mapping** box. If you did the //Make DDR2 External// step then the target memory region **must** read **mig_7series_0**. Scroll down to check if this applies to all rows. If for any region it does not say **mig_7series_0**, then click on the row under the **Memory Region** column and select **mig_7series_0**. {{:nexys4-ddr:server_28.jpg?nolink|}} ==== Setting PHY Link Speed ==== 30. Open the //system.mss// file within the //echo_server_bsp// folder and click **Modify this BSP's Settings**. {{:nexys4-ddr:server_30.jpg?nolink|}} Select //lwip140//, then expand the //temac_adapter_options// and find //phy_link_speed// in the list. Change the value of //phy_link_speed// to **CONFIG_LINKSPEED1000** and press OK. {{:nexys4-ddr:server_31.jpg?nolink|}} ==== Programming FPGA with Bit File ==== 31. Make sure that the Nexys Video is turned on and connected to the host PC with the provided micro USB cable plugged into the Prog port on the Nexys Video. On the main toolbar, click **Xilinx Tools>>Program FPGA** Make sure that the //Hardware Platform// is selected as **design_1_wrapper_hw_platform_0**. In the software configuration box, under //ELF File to Initialize in Block RAM// column, the row option must read **bootloop**. If not, click on the row and select **bootloop**. Now click on Program. {{:nexys4-ddr:server_29.jpg?nolink|}} ==== Setting up the SDK Serial Console and Running the Server ==== 32. Right click on the //echo_server// project folder and select **Run As >> Run Configurations** {{:nexys4-ddr:server_32.jpg?nolink|}} **Move the USB plug from the Prog port on your board to the UART port**. Now go to the //STDIO Connection// tab and check the //Connect STDIO to Console// check-box. Click //Apply//, then click //Run//. {{:nexys4-ddr:server_33.jpg?nolink|}} ==== Running the Server ==== 33. In the console window at the bottom of the screen the details of the connection will be displayed. {{:nexys4-ddr:server_34.jpg?nolink|}} ==== Testing the Server with Tera Term ==== 34. Connect your PC to your Nexys Video using an Ethernet cable. 35. In order to connect to the echo server, you must set up your Ethernet connection with a static IP address. To do this: * Right click your internet connection and click //Open Network and Sharing Center//. {{:nexys4-ddr:server_35.jpg?nolink|}} * Find the Ethernet Connection to your Nexys Video. It should be an unidentified network. Click //Local Area Connection//. {{:nexys4-ddr:server_36.jpg?nolink|}} * Click //Properties//. {{:nexys4-ddr:server_37.jpg?nolink|}} * Select //Internet Protocol Version 4 (TCP/IPv4)// and click //Properties//. {{:nexys4-ddr:server_38.jpg?nolink|}} * Click the //Use the following IP address:// bullet and type in an IP address 192.168.1.XX, where XX is a value between 2 and 255, but not 10. **This IP must not be the same as another already on your network**. Make sure to click within the //Subnet mask// field to get the 255.255.255.0 mask to autofill. Click Ok and you will have a static IP address. {{:nexys4-ddr:server_39.jpg?nolink|}} 36. Open Tera Term and type in the following info and click Ok. {{:nexys4-ddr:server_40.jpg?nolink|}} 37. Type anything into the console and press Enter. The echo server will echo back your input and display it in the console. //You can go to Setup>Terminal and change the settings below for a more traditional echo server format// {{:nexys4-ddr:11.jpg?nolink|}}