====== Arty - Getting Started with Microblaze Servers ====== {{ :arty:arty-obl-1000.png?nolink&500 |}} ===== Overview ===== This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the [[arty:gsmb|Getting Started with Microblaze]] guide by making use of the on-board Ethernet port and GPIOs for the Arty FPGA board. At the end of this tutorial you will have a comprehensive hardware design for Arty that makes use of various Hardware ports on the Arty which are managed by the Microblaze Softcore Processor block. ---- ===== Prerequisites ===== === Skills === * **Familiarity with Vivado** === Hardware === * **Arty FPGA Board** * **Micro USB Cable** * //for UART communication and JTAG programming// * **Ethernet Cord** === Software === * **Xilinx Vivado 2015.X with the SDK package.** * **Serial Terminal Application** * //Tera Term is used in this tutorial// === Board Support Files === * **Arty Support Files** * //These files will describe GPIO interfaces on your board and make it easier to select your board in the initial design setup and add GPIO IP blocks in the block design// * //Follow this Wiki guide **[[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]** on how to install Board Support Files for Vivado 2015.X// ----- ===== Introduction ===== Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server. ----- ===== General Design Flow ===== I. Vivado * Open Vivado and select Arty board * Create an new Vivado Project * Create empty block design workspace inside the new project * Add required IP blocks using the IP integrator tool and build Hardware Design * Validate and save block design * Create HDL system wrapper * Run design Synthesis and Implementation * Generate Bit File * Export Hardware Design including the generated bit stream file to SDK tool * Launch SDK Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado. II. SDK * Create new application project and select default Hello World template * Program FPGA * Run configuration by selecting the correct UART COM Port and Baud Rate ----- ===== Tutorial ===== ==== 1. Creating a New Project ==== >1.1) Open up Vivado and click **Create New Project** to open Vivado's New Project wizard. > >{{:basys3:basys3_screen_shot_2015-6-10_1.png?nolink&500|}} >1.2) A new window will open up, click **Next** and you'll see the screen below. Name your project (no spaces!) and choose your project saving directory before clicking **Next**. Underscores are a good substitute for empty spaces. > >{{:basys3:basys3_screen_shot_2015-6-10_2.png?nolink&500|}} >1.3) We will be building this project from the ground up and adding our own sources so we will want to create an RTL project. Select **RTL Project** and leave the **Do not specify sources** box unchecked. Click **Next**. > >{{:basys3:basys3_screen_shot_2015-6-10_3.png?nolink&500|}} >1.4) If you have followed the Board Support File Wiki guide then click next and select **Boards**. From the filter options make required selections for Vendor, Display Name and Board Revision. **Arty** should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. > >{{:arty:1.jpg?nolink500|}} >1.5) Click **Next**, a summary of the new project design sources and target device is displayed. Click **Finish**. > >{{:vivado:mig_3.jpg?500|}} At this point you have successfully created a project that will properly communicate with the Arty. ---- ====2. Creating New Block Design ==== This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design. {{:genesys2:gsmb3.jpg?nolink&500|}} >2.1) On the left you should see the Flow Navigator. Select **Create Block Design** under the IP Integrator. Give a name to your design (without any empty spaces) and click **Ok**. > >{{:genesys2:gsmb4.jpg?nolink&500|}} > >You have created a new block design. > >{{:genesys2:gsmb5.jpg?nolink&500|}} ----- ====3. Adding the clock and DDR3 Component==== >3.1) Click the **Board** tab (Highlighted in orange below) > >{{:arty:gsmb3.jpg?direct&500|}} > >This list contains all of the components defined in the board file you installed before. These are already configured to work with several Vivado IPs. >3.2) Click and drag the **System Clock** component onto the empty block design. Vivado will automatically connect the system clock to a new Clocking Wizard block. > >{{:arty:gsmb4.jpg?direct&500|}} >3.3) Double click the **Clocking Wizard** block to customize it. Click on the **Output Clocks** tab and change **clk_out1** to "166.667" MHz. Enable **clk_out2** and set it to "200.0" MHz. Enable **clk_out3** and set it to "25" MHz. Set the **reset type** to **Active Low**. Then click **OK** to close this window. > >{{:arty:gsmbs5.jpg?direct&700|}} >3.4) Click and drag the **DDR3 SDRAM** component onto the empty block design. Vivado will automatically connect the DDR3 SDRAM and some dummy clock ports to the MIG IP. > >{{:arty:gsmb6.jpg?direct&500|}} >3.5) **Delete** the **clk_ref_i** and **sys_clk_i** ports by clicking them and pressing the **Delete** key, or by right clicking them and selecting Delete. > >{{:arty:gsmb8.jpg?direct&500|}} >3.6) Connect **clk_out1** to **sys_clk_i** on the MIG block. Connect **clk_out2** to **clk_ref_i**. > >{{:arty:gsmb7.jpg?direct&500|}} >3.7) Click **Run Connection Automation** in the green banner above. Click **Ok**. > >{{:genesys2:gsmb9.jpg?nolink&500|}} > >Vivado will connect your system reset to sys_rst on the MIG. **Connect** this new reset port to the **resetn** input on the Clock Wizard block. > >{{:arty:server_14.png?nolink&200|}} ----- ====4. Adding the Microblaze Processor & Configuration ==== >4.1) Click the {{:genesys2:addip.jpg?nolink|}} **Add IP** button and search for **Microblaze**. > >{{:genesys2:gsmb6.jpg?nolink&400|}} > >Double click **Microblaze** to add it to your block design. > >{{:genesys2:gsmb10.jpg?nolink&500|}} >4.2) Click **Run Block Automation** to open the Block automation for the Microblaze processor. > >Here you can choose how much memory to give your Microblaze processor. **Configure the options** to match the picture below, then click **OK**. Make sure that you check the **interrupt Controller** box and set the Clock Connection to **/mig_7series_0/ui_clk**. > >{{:arty:gsmbs1.jpg?direct&700|}} >4.3) Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. **Do not click on Run Connection Automation yet.** > >{{:arty:gsmbs2.jpg?direct&700|}} ==== 5. Adding the Peripherals ==== >5.1) Go into the **Boards** tab again and find the **USB UART** component. **Click and drag** this onto the block design to add the Uartlite block to your design. >5.2) Find the **Ethernet MII** and **drag this onto the block design** to add the Ethernet block to your design. > >{{:arty:gsmbs3.jpg?direct&700|}} >5.3) Click the {{:genesys2:addip.jpg?nolink|}} **Add IP** button and search for **Timer**. Double click **AXI Timer** to add it to your block design. > >{{:genesys2:gsmbs16.jpg?nolink&300|}} >5.4) Click **Run Connection Automation** in the green banner. Check the **All Automation** checkbox and click **OK**. You might now get a warning about obsolete automations. Just click **OK**. > >{{:arty:gsmbs4.jpg?direct&700|}} ---- ==== 6. Routing the Last Connections ==== >6.1) Route **interrupt** on the //AXI Timer// block to **In0[0:0]** on the //Concat// block. Next route **ip2intc_irpt** on the //AXI EthernetLite// block to **In1[0:0]** on the //Concat// block. > >{{:nexys4-ddr:server_13.jpg?nolink500|}} >6.2) Right click somewhere in the background (white space) of your design and click **Create Port...**, or use the shortcut, Ctrl-K. Name this port "eth_ref_clk" and change the options to the one in the picture below. Click **OK** once finished. > >{{:nexys4-ddr:server_15.jpg?nolink500|}} >6.3) Connect this **eth_ref_clk** pin to **clk_out3** on the //Clocking Wizard// block. > >{{:arty:gsmbs6.jpg?direct&500|}} ====7. Validating Design and making an HDL Wrapper ==== >7.1) Click the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** button to rearrange your block design. > >{{:arty:gsmbs7.jpg?direct&700|}} >7.2) Select {{:genesys2:validate.jpg?nolink|}} **Validate Design**. This will check for design and connection errors. >7.3) After the design validation step we will proceed with creating a HDL System Wrapper. Click on the **Sources** tab and find your block design. > >{{:genesys2:gsmb16.jpg?nolink&500|}} >7.4) Right click on your block design and click **Create HDL Wrapper**. **Let Vivado manage wrapper and auto-update** and click **OK**. > >{{:genesys2:gsmb17.jpg?nolink&500|}} > >This will create a top module in VHDL and will allow you to generate a bitstream. ----- ====8. Constraining Eth_ref_clk ==== >8.1) We must now connect the eth_ref_clk pin to the correct pin on the FPGA by creating an XDC file. Under the //Design// window, select the **Sources** tab. Expand the //contraints// folder, right click on //constr// and click **Add Sources...** > >{{:nexys4-ddr:server_19.jpg?nolink500|}} >8.2) Select Add or create constraints and click **Next**. > >{{:nexys4-ddr:server_20.jpg?nolink500|}} >8.3) Click **Create File...**, name your new constraints file and click **OK** and then **Finish**. > >{{:nexys4-ddr:server_21.jpg?nolink500|}} >8.4) Open your new constraints file and paste the following line of code in it: set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clk >8.5) Save the XDC file when you are finished. ----- ====8. Generating Bit File ==== >8.1) In the top toolbar in Vivado, click {{:genesys2:generate.jpg?nolink|}} **Generate Bitstream**. This can also be found in the //Flow Navigator// panel on the left, under //Program and Debug//. >If you haven't already saved your design, you will get a prompt to save the block design. >8.2) The bit file generation will begin. The tool will run //Synthesis// and //Implementation//. After both synthesis and implementation have been successfully completed, the bit file will be created. You will find a status bar of Synthesis and Implementation running on the top right corner of the project window. > >This process can take anywhere from **5 to 60 minutes** depending on your computer. >8.3) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click **Cancel**. ----- ====9. Exporting Hardware Design to SDK ==== >9.1) On the main toolbar, click **File** and select **Export Hardware**. Check the box to **Include Bitstream** and click **OK**. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK. > >{{:genesys2:gsmb18.jpg?nolink|}} > >A new file directory will be created under **echo_server.SDK** similar to the Vivado hardware design project name. Two other files, //.sysdef// and //.hdf// are also created. This step essentially creates a new SDK Workspace. >9.2) On the main toolbar, click **File->Launch SDK**. Leave both of the dropdown menus as their default //Local to Project// and click **OK**. This will open Xilinx SDK and import your hardware. > >{{:genesys2:gsmb19.jpg?nolink&300|}} ----- ====10. Inside Xilinx SDK ==== >10.1) The HW design specification and included IP blocks are displayed in the //system.hdf// file. Xilinx SDK is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory. > >From this point, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK. > >{{:genesys2:gsmbs17.jpg?nolink&700|}} >10.2) Within the //Project Explorer// tab on the left, you can see your hardware platform. > >**system** is the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information. ----- ====11. Creating New Application Project in SDK ==== >11.1) Click the {{:genesys2:new.jpg?nolink|}} **New** dropdown arrow and select **Application Project**. > >{{:genesys2:gsmbs18.jpg?nolink&500|}} > >Give your project a name that has no empty spaces and click **Next**. >11.2) Select **lwIP Echo Server** from the list of templates and click **OK**. > >{{:genesys2:gsmbs19.jpg?nolink&500|}} >You will see two new folders in the **Project Explorer** panel. > -- **echo_server** which contains all the binaries, .C and .H (Header) files > -- **echo_server_bsp** which is the board support folder > >**echo_server** is our main working source folder. This also contains an important file shown here which is **lscript.ld**. This is a Xilinx auto generated linker script file. Double click on this file to open. >11.3) Back in the **Project Explorer**, double click and open **system.mss** under the **echo_server_bsp** folder. Click **Modify this BSP's Settings**. > >{{:genesys2:gsmbs20.jpg?nolink&600|}} >11.4) Click **lwip141** then find **temac_adapter_options** and click the arrow. Find **phy_link_speed** and change the Value to **CONFIG_LINKSPEED100**. Click **OK**. > >{{:genesys2:gsmbs21.jpg?nolink&600|}} ----- ====12. Programming FPGA with Bit File ==== >12.1) Make sure that the Arty is connected to the host PC via the micro USB port. If properly connected, the red power LED should turn on. On the top toolbar, click the {{:genesys2:programfpga.jpg?nolink|}} **Program FPGA** button. >12.2) Click **Program** to program your FPGA with your hardware design. > >{{:genesys2:gsmb24.jpg?nolink&500|}} ----- ====13. Setting up UART Terminal==== >13.1) Open up a Serial Terminal application (Tera Term). Connect to the Arty UART port with a baud rate of 9600. This baud rate can be altered in your block design by double clicking the Uartlite block. > >{{:genesys2:gsmb25.jpg?nolink&500|}} ----- ====1. Program the Microblaze Processor==== >14.1) Make sure you have your Arty plugged into a router before beginning. >14.2) Back in SDK, select your **echo_server** project and click the {{:genesys2:run.jpg?nolink|}} **Run As...** button. Select **Launch on Hardware (System Debugger)** and click **OK**. > >{{:genesys2:gsmbs22.jpg?nolink&300|}} >14.3) In the console window at the bottom of the screen the details of the connection will be displayed. This shows all three phy speed link settings. > >{{:learn:programmable-logic:tutorials:arty-getting-started-with-microblaze-servers:arty_echo_2017_2_number_1.jpg?600|}} ---- ==== 15. Testing the Server with Tera Term ==== >15.1) Connect your PC to your Zybo using an Ethernet cable. **If using a router, watch the UART console to find out the IP of the Zybo echo server, and connect to that IP address. Setting up the connection as static is unnecessary.** >15.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this: >15.2.1) Right click your internet connection and click **Open Network and Sharing Center**. > >{{:nexys4-ddr:server_35.jpg?direct&500|}} >15.2.2) Find the Ethernet Connection to your Zybo. It should be an unidentified network. Click **Ethernet**. > >{{:learn:programmable-logic:tutorials:zybo-getting-started-with-zynq-server:echo_server_zynq_12.jpg?direct&600|}} >15.2.3) Click **Properties**. > >{{:nexys4-ddr:server_37.jpg?direct&500|}} >15.2.4) Select **Internet Protocol Version 4 (TCP/IPv4)** and click **Properties**. > >{{:nexys4-ddr:server_38.jpg?direct&500|}} >15.2.5) Click the **Use the following IP address:** bullet and type in an IP address "192.168.1.XX", where XX is a value between 2 and 255, but not 10. **This IP must not be the same as another already on your network**. Make sure to click within the //Subnet mask// field to get the 255.255.255.0 mask to autofill. Click **Ok** and you will have a static IP address. > >{{:nexys4-ddr:server_39.jpg?direct&500|}} >15.3) Open Tera Term and type in the following info and click **Ok**. > >{{:learn:programmable-logic:tutorials:zybo-getting-started-with-zynq-server:echo_server_zynq_4.jpg?direct&600|}} >15.4) Type anything into the console and press your keyboard's Enter key. The echo server will echo back your input and display it in the console. > >//You can go to Setup->Terminal and change the settings below for a more traditional echo server format// > >{{:nexys4-ddr:11.jpg?direct&500|}} > Remember to go back into **Open Network and Sharing Center** > Select **Internet Protocol Version 4 (TCP/IPv4)** and click **Properties**. > Select **obtain an IP address automatically** ----- {{tag>learn programmable-logic tutorial arty microblaze-servers}}